FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 26
![IC CTRLR SUPER I/O MULTI 100-QFP](/photos/6/82/68212/qfp100-g1_pkg_sml.jpg)
FDC37C665GT-MS
Manufacturer Part Number
FDC37C665GT-MS
Description
IC CTRLR SUPER I/O MULTI 100-QFP
Manufacturer
SMSC
Datasheet
1.FDC37C665GT-MS.pdf
(152 pages)
Specifications of FDC37C665GT-MS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
35mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1007
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FDC37C665GT-MS
Manufacturer:
Microchip Technology
Quantity:
10 000
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STATUS REGISTER B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state
of several disk interface pins, in PS/2 and Model
PS/2 Mode
BIT 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 1 MOTOR ENABLE 1
Active high status of the MTR1 disk interface
output pin. This bit is low after a hardware reset
and unaffected by a software reset.
BIT 2 WRITE GATE
Active high status of the WGATE disk interface
output.
BIT 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes
this bit to change state.
RESET
COND.
7
1
1
6
1
1
DRIVE
SEL0
5
0
TOGGLE
WDATA
4
0
26
30 modes. The SRB can be accessed at any
time when in PS/2 mode. In the PC/AT mode
the data bus pins D0 - D7 are held in a high
impedance state for a read of address 3F1.
BIT 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes
this bit to change state.
BIT 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of
the DOR (address 3F2 bit 0). This bit is cleared
after a hardware reset, it is unaffected by a
software reset.
BIT 6 RESERVED
Always read as a logic "1".
BIT 7 RESERVED
Always read as a logic "1".
TOGGLE
RDATA
3
0
WGATE
2
0
MOT
EN1
1
0
MOT
EN0
0
0
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