FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 45
![IC CTRLR SUPER I/O MULTI 100-QFP](/photos/6/82/68212/qfp100-g1_pkg_sml.jpg)
FDC37C665GT-MS
Manufacturer Part Number
FDC37C665GT-MS
Description
IC CTRLR SUPER I/O MULTI 100-QFP
Manufacturer
SMSC
Datasheet
1.FDC37C665GT-MS.pdf
(152 pages)
Specifications of FDC37C665GT-MS
Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
35mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1007
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FDC37C665GT-MS
Manufacturer:
Microchip Technology
Quantity:
10 000
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If the last sector to be transferred is a partial
sector, the host can stop transferring the data in
mid-sector, and the FDC will continue to
complete the sector as if a hardware TC was
received.
implicit functions and TC is that they return
"abnormal termination" result status.
status indications can be ignored if they were
expected.
Note that when the host is sending data to the
FIFO of the FDC, the internal sector count will
be complete when the FDC reads the last byte
from its side of the FIFO. There may be a delay
in the removal of the transfer request signal of
up to the time taken for the FDC to read the last
16 bytes from the FIFO. The host must tolerate
this delay.
The only difference between these
Such
45
Result Phase
The
beginning of the result phase. For each of the
commands, a defined set of result bytes has to
be read from the FDC before the result phase is
complete. These bytes of data must be read out
for another command to start.
RQM and DIO must both equal "1" before the
result bytes may be read. After all the result
bytes have been read, the RQM and DIO bits
switch to "1" and "0" respectively, and the CB bit
is cleared, indicating that the FDC is ready to
accept the next command.
generation
of
FINT
determines
the
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