FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 78

• Manufacturer Part Number: FDC37C665GT-MS
• Description: IC CTRLR SUPER I/O MULTI 100-QFP
• Manufacturer: SMSC

Specifications of FDC37C665GT-MS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 35mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1007

The
incorporate two full function UARTs. They are
compatible with the NS16450, the 16450 ACE
registers and the NS16550A.
perform serial-to-parallel conversion on received
characters and parallel-to-serial conversion on
transmit characters.
independently programmable from 115.2K baud
down to 50 baud.
programmable for 1 start; 1, 1.5 or 2 stop bits;
even, odd, sticky or no parity; and prioritized
interrupts.
programmable baud rate generator that is
capable of dividing the input clock or crystal by
a number from 1 to 65535. The UARTs are also
capable of supporting the MIDI data rate. Refer
to the FDC37C665GT Configuration Registers
and the FDC37C666GT Hardware
*NOTE: DLAB is Bit 7 of the Line Control Register
FDC37C665GT
The UARTS each contain a
DLAB*
X
X
X
X
X
X
X
0
0
0
1
1
The character options are
The data rates are
and
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 34 - Addressing the Serial Port
FDC37C666GT
The UARTS
A1
0
0
0
1
1
1
0
0
1
1
0
0
SERIAL PORT (UART)
A0
0
0
1
0
0
1
0
1
0
1
0
1
78
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
Configuration description for information on
disabling, power down and changing the base
address of the UARTS. The interrupt from a
UART is enabled by programming OUT2 of that
UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below.
addresses of the serial ports are defined by the
configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37C665GT/666GT
contains two serial ports, each of which contain
a register set as described below.
REGISTER NAME
registers
(see
Configuration
The base