FDC37C665GT-MS SMSC, FDC37C665GT-MS Datasheet - Page 74

• Manufacturer Part Number: FDC37C665GT-MS
• Description: IC CTRLR SUPER I/O MULTI 100-QFP
• Manufacturer: SMSC

Specifications of FDC37C665GT-MS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 35mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1007

types,
compensation values.
When both GAP and WGATE bits of the
PERPENDICULAR MODE COMMAND are both
programmed to "0" (Conventional mode), then
D0, D1, D2, D3, and D4 can be programmed
independently to "1" for that drive to be set
automatically to Perpendicular mode.
mode the following set of conditions also apply:
1. The GAP2 written to a perpendicular drive
2. The write pre-compensation given to a
LOCK
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added.
used by the FDC routines, and application
software should refrain from using it.
application calls for the FIFO to be disabled
then the CONFIGURE command should be
used.
during a write operation will depend upon the
programmed data rate.
perpendicular mode drive will be 0ns.
nor
having
This command should only be
WGATE
0
0
1
1
to
GAP
change
Table 32 - Effects of WGATE and GAP Bits
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
write
MODE
In this
If an
pre-
74
LENGTH OF
3. For
Note: Bits D0-D3 can only be overwritten when
Software
following
MODE COMMAND:
1. "Software" resets (via the DOR or DSR
2. "Hardware" resets will clear all bits ( GAP,
The LOCK command defines whether the
EFIFO, FIFOTHR, and PRETRK parameters of
the CONFIGURE command can be RESET by
the DOR and DSR registers. When the LOCK
bit is set to logic "1" all subsequent "software
RESETS by the DOR and DSR registers will not
change the previously set parameters to their
default values. All "hardware" RESET from the
RESET pin will set the LOCK bit to logic "0" and
their default values. A status byte is returned
immediately after issuing a a LOCK command.
return the EFIFO, FIFOTHR, and PRETRK to
FORMAT
22 Bytes
22 Bytes
22 Bytes
41 Bytes
FIELD
GAP2
conventional mode drives any data written
will be at the currently programmed write
pre-compensation.
registers) will only clear GAP and WGATE
bits to "0". D0-D3 are unaffected and retain
their previous value.
WGATE
conventional mode.
OW is programmed as a "1".
If either GAP or WGATE is a "1" then
D0-D3 are ignored.
D0-D3
effect
and
and
hardware
PORTION OF
WRITTEN BY
WRITE DATA
OPERATION
on
programmed
19 Bytes
38 Bytes
D0-D3)
0 Bytes
0 Bytes
GAP 2
the
resets
PERPENDICULAR
to
"0",
to
have
"0"
i.e
the
for
all