DP83916VF National Semiconductor, DP83916VF Datasheet - Page 18

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

3 0 Buffer Management
All RRA registers are concatenated with the URRA register
for generating the full 23-bit address
The resource descriptors that the system writes to the RRA
consists
RXrsrc buff ptr1
RXrsrc buff wc1 The fields must be contiguous (they can-
not straddle the end points) and are written in the order
shown in Figure 3-8 The ‘‘0’’ and ‘‘1’’ in the descriptors
denote the least and most significant portions for the Buffer
Pointer and Word Count The first two fields supply the
23-bit starting location of the Receive Buffer Area (RBA)
and the second two define the number of 16-bit words that
the RBA occupies Note that a restriction applies to the
Buffer Pointer and Word Count The Buffer Pointer must be
pointing to a word boundary Note also that the descriptors
must be properly aligned in the RRA as discussed in Section
3 3
After configuring the RRA the RRA Read command (setting
RRRA bit in the Command register) may be given This
command causes the SONIC-16 to read the RRA descriptor
in a single block operation and load the following registers
(see Section 4 2 for register mnemonics)
CRBA0 register
CRBA1 register
RBWC0 register
RBWC1 register
When the command has completed the RRRA bit in the
Command register is reset to ‘‘0’’ Generally this command
is only issued during initialization At all other times the RRA
is automatically read as the SONIC-16 finishes using an
RBA
3 4 4 3 Initializing The RDA
To accept multiple packets from the network the receive
packet descriptors must be linked together via the
RXpkt link fields Each link field must be written with a 15-bit
(A15 –A1) pointer to locate the beginning of the next de-
scriptor in the list The LSB of the RXpkt link field is the End
of List (EOL) bit and is used to indicate the end of the de-
scriptor list EOL
the first or middle descriptors The RXpkt in use field indi-
cates whether the descriptor is owned by the SONIC-16
The system writes a non-zero value to this field when the
descriptor is available and the SONIC-16 writes all ‘‘0’s’’
of
FIGURE 3-8 RRA Initialization
four
e
1 for the last descriptor and EOL
RXrsrc buff ptr0
RXrsrc buff ptr1
RXrsrc buff wc0
RXrsrc buff wc1
(3)
fields
RXrsrc buff wc0
(1)
RXrsrc buff ptr0
(Continued)
TL F 11722–15
and
e
0 for
(2)
(4)
18
when it finishes using the descriptor At startup the Current
Receive Descriptor Address (CRDA) register must be load-
ed with the address of the first RXpkt status field in order for
the SONIC-16 to begin receive processing at the first de-
scriptor An example of two descriptors linked together is
shown in Figure 3-9 The fields initialized by the system are
displayed in larger type The other fields are written by the
SONIC-16 after a packet is accepted The RXpkt in use
field is first written by the system and then by the SONIC-
16 Note that the descriptors must be aligned properly as
discussed in section 3 3 Also note that the URDA register is
concatenated with the CRDA register to generate the full
23-bit address
3 4 4 4 Initializing the Lower Boundary of the RBA
A ‘‘false bottom’’ is set in the RBA by loading the End Of
Buffer Count (EOBC) register with a value equal to the maxi-
mum size packet in words (16 bits) that may be received
This creates a lower boundary in the RBA Whenever the
Remaining Buffer Word Count (RBWC0 1) registers decre-
ment below the EOBC register the SONIC-16 buffers the
next packet into another RBA This also guarantees that a
packet is always contiguously buffered into a single Receive
Buffer Area (RBA) The SONIC-16 does not buffer a packet
into multiple RBAs
After a hardware reset the EOBC register is automatically
initialized to 2F8h (760 words or 1520 bytes)
Sometimes it may be desired to buffer a single packet per
RBA When doing this it is important to set EOBC and the
buffer size correctly The suggested practice is to set EOBC
to a value that is at least 2 bytes less than the buffer size
FIGURE 3-9 RDA Initialization Example
TL F 11722 – 16