DP83916VF National Semiconductor, DP83916VF Datasheet - Page 82
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DP83916VF
Manufacturer Part Number
DP83916VF
Description
IC CTRLR ORIENT NETWK IN 132PQFP
Manufacturer
National Semiconductor
Series
SONIC™r
Datasheet
1.DP83916VF.pdf
(96 pages)
Specifications of DP83916VF
Controller Type
Network Interface Controller (NIC)
Interface
Bus
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Supply
-
Voltage - Supply
-
Operating Temperature
-
Other names
*DP83916VF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83916VF
Manufacturer:
National
Quantity:
226
Part Number:
DP83916VF
Manufacturer:
NS/国半
Quantity:
20 000
7 0 AC and DC Specifications
BUS REQUEST TIMING BMODE
Note 1 A block transfer by the SONIC-16 can be pre-empted from the bus by deasserting HLDA provided HLDA is asserted T46 before the rising edge of the last
T2 in the current access
Note 2 The assertion edge for HOLD is dependent upon the PH bit in the DCR2 The default situation is shown wih a solid line in the timing diagram T43 and T44
apply for both modes Also if HLDA is asserted when the SONIC-16 wants to acquire the bus HOLD will not be asserted until HLDA has been deasserted first
Note 3 S
Note 4 This timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive
these lines without contention
Note 5 For specific timings on these signals (driven by the SONIC-16) see the memory read and memory write timing diagrams on previous pages
Number
T43
T44
T45
T46
T51
T52
T53
T55
T55a
T55b
k
2 0
l
will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation
BSCK to HOLD High (Note 2)
BSCK to HOLD Low (Note 2)
HLDA Asynchronous Setup Time to BSCK
HLDA Deassert Setup Time (Note 1)
BSCK to Address ADS MWR DS ECS
USR
(Note 4)
BSCK to Data TRI-STATE (Note 4)
BSCK to USR
BSCK to Bus Status
Idle to Non-Idle
BSCK to Bus Status
Non-Idle to Idle (Note 3)
S
k
2 0
k
1 0
l
e
Hold from BSCK
l
0
and EXUSR
k
1 0
Parameter
l
Valid
(Continued)
k
3 0
l
TRI-STATE
82
Min
10
5
5
20 MHz
Max
25
22
52
68
50
40
40
Units
TL F 11722 – 69
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns