DP83916VF National Semiconductor, DP83916VF Datasheet - Page 53

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

Figures 5-5 and 5-6 show the National Intel (BMODE
5 0 Bus Interface
5 4 1 Acquiring The Bus
The SONIC-16 requests the bus when 1) its FIFO threshold
has been reached or 2) when the descriptor areas in memo-
ry (i e RRA RDA CDA and TDA) are accessed Note that
when the SONIC-16 moves from one area in memory to
another (e g RBA to RDA) it always deasserts its bus re-
quest and then requests the bus again when accessing the
next area in memory
The SONIC-16 provides two methods to acquire the bus for
compatibility with National Intel or Motorola type microproc-
essors These two methods are selected by setting the
proper level on the BMODE pin
and Motorola (BMODE
tions of each mode follows For both modes when the
SONIC-16 relinquishes the bus there is an extra holding
state (Th) for one bus cycle after the last DMA cycle (T2)
This assures that the SONIC-16 does not contend with an-
other bus master after it has released the bus
BMODE
The National Intel processors require a 2-way handshake
using a HOLD REQUEST HOLD ACKNOWLEDGE protocol
( Figure 5-5 ) When the SONIC-16 needs to access the bus
it issues a HOLD REQUEST (HOLD) to the microprocessor
The microprocessor responds with a HOLD ACKNOWL-
EDGE (HLDA) to the SONIC-16 The SONIC-16 then begins
its memory transfers on the bus As long as the CPU main-
tains HLDA active the SONIC-16 continues until it has fin-
ished its memory block transfer The CPU however can
preempt the SONIC-16 from finishing the block transfer by
deasserting HLDA before the SONIC-16 deasserts HOLD
This allows a higher priority device to preempt the SONIC-
16 from continuing to use the bus The SONIC-16 will re-
quest the bus again later to complete any operation that it
was doing at the time of preemption
e
0
e
1) bus request timing Descrip-
(Continued)
FIGURE 5-5 Bus Request Timing BMODE
e
0)
53
As shown in Figure 5-5 the SONIC-16 will assert HOLD to
either the falling or rising edge of the bus clock (BSCK) The
default is for HOLD to be asserted on the falling edge Set-
ting the PH bit in the DCR2 (see Section 4 3 7) causes
HOLD to be asserted
(shown by the dotted line) Before HOLD is asserted the
SONIC-16 checks the HLDA line If HLDA is asserted
HOLD will not be asserted until after HLDA has been deas-
serted first
BMODE
The Motorola protocol requires a 3-way handshake using a
BUS REQUEST BUS GRANT and BUS GRANT AC-
KNOWLEDGE handshake ( Figure 5-6 ) When using this
protocol the SONIC-16 requests the bus by lowering BUS
REQUEST (BR) The CPU responds by issuing BUS
GRANT (BG) Upon receiving BG the SONIC-16 assures
that all devices have relinquished control of the bus before
using the bus The following signals must be deasserted
before the SONIC-16 acquires the bus
Deasserting BGACK indicates that the previous master has
released the bus Deasserting AS indicates that the previ-
ous master has completed its cycle and deasserting
DSACK0 1 and STERM indicates that the previous slave
has terminated its connection to the previous master The
SONIC-16 maintains its mastership of the bus until it deas-
serts BGACK It can not be preempted from the bus
BGACK
AS
DSACK0 1
STERM (Asynchronous Mode Only)
e
1
e
0
bus clock later on the rising edge
TL F 11722 – 27