DP83916VF National Semiconductor, DP83916VF Datasheet - Page 65

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

5 0 Bus Interface
5 4 7 2 Slave Cycle for BMODE
The system accesses the SONIC-16 by driving SAS CS
SWR and RA
bus cycle but the SONIC-16 will not actually start a slave
cycle until CS has been sampled low and SAS has been
sampled high CS should not be asserted low before the
falling edge of SAS as this will cause improper slave opera-
tion CS may be asserted low however before the rising
edge of SAS In this case it is suggested that SAS be driven
high within one bus clock after the falling edge of CS Be-
tween one and two bus clocks after the assertion of CS
once SAS has been driven high SMACK will be driven low
to signify that the SONIC-16 has started the slave cycle
Although CS is an asynchronous input meeting its setup
time (as shown in Figures 5-23 and 5-24 ) will guarantee that
SMACK which is asserted off a falling edge will be assert-
ed 1 bus clock after the falling edge that CS was clocked in
on This is assuming that the SONIC-16 is not a bus master
when CS is asserted If the SONIC-16 is a bus master then
when CS is asserted the SONIC-16 will complete its current
master bus cycle and get off the bus temporarily (see Sec-
tion 5 4 8) In this case SMACK will be asserted 5 bus
clocks after the falling edge that CS was clocked in on This
is assuming that there were no wait states in the current
master mode access Wait states will increase the time for
SMACK to go low by the number of wait states in the cycle
k
5 0
l
These signals will be sampled each
(Continued)
e
0
FIGURE 5-23 Register Read BMODE
65
If the slave access is a read cycle ( Figure 5-23 ) then the
data will be driven off the same edge as SMACK If it is a
write cycle ( Figure 5-24 ) then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK In either
case RDYo is driven low 2
terminate the slave cycle For a read cycle the assertion of
RDYo indicates valid register data and for a write cycle the
assertion indicates that the SONIC-16 has latched the data
The SONIC-16 deasserts RDYo SMACK and the data if the
cycle is a read cycle at the falling edge of SAS or the rising
edge of CS depending on which is first
Note 1 The SONIC-16 transfers data only on lines D
Note 2 For multiple register accesses CS can be held low and SAS can be
Note 3 If memory request (MREQ) follows a chip select (CS) it must be
Note 4 When CS is deasserted it must remain deasserted for at least one
Note 5 The way in which SMACK is asserted due to CS is not the same as
mode accesses
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS) In this case SMACK will be driven low
due to SAS going high since CS has already been asserted Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ Section 5 4 8)
asserted at least 2 bus clocks after CS is deasserted Both CS and
MREQ must not be asserted concurrently
bus clock
the way in which SMACK is asserted due to MREQ The assertion of
SMACK is dependent upon both CS and SAS being low not just CS
This is not the same as the case for MREQ (see Section 5 4 8) The
assertion of SMACK in these two cases should not be confused
e
0
bus clocks after SMACK to
k
15 0
l
TL F 11722 – 49
during slave