DP83916VF National Semiconductor, DP83916VF Datasheet - Page 7

• Manufacturer Part Number: DP83916VF
• Description: IC CTRLR ORIENT NETWK IN 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83916VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Bus
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Operating Temperature: -
• Other names: *DP83916VF

1 0 Functional Description
Serializer After data has been written into the 32-byte
transmit FIFO the serializer reads byte wide data from the
FIFO and sends a NRZ data stream to the Manchester en-
coder The rate at which data is transmitted is determined
by the transmit clock (TXC) The serialized data is transmit-
ted after the SFD
Preamble Generator The preamble generator prefixes a
62-bit alternating ‘‘1 0’’ pattern and a 2-bit ‘‘1 1’’ SFD pat-
tern at the beginning of each packet This allows receiving
nodes to synchronize to the incoming data The preamble is
always transmitted in its entirety even in the event of a colli-
sion This assures that the minimum collision fragment is 96
bits (64 bits of normal preamble and 4 bytes or rather 32
bits of the JAM pattern)
CRC Generator The CRC generator calculates the 4-byte
FCS field from the transmitted serial data stream If en-
abled the 4-byte FCS field is appended to the end of the
transmitted packet (section 2 6)
Jam Generator The Jam generator produces a 4-byte pat-
tern of all 1’s to assure that all nodes on the network sense
the collision When a collision occurs the SONIC-16 stops
transmitting data and enables the Jam generator If a colli-
sion occurs during the preamble the SONIC-16 finishes
transmitting the preamble before enabling the Jam genera-
tor (see Preamble Generator above)
1 3 BYTE ORDERING
The SONIC-16 will operate with 16-bit wide memory The
SONIC-16 provides both Little Endian and Big Endian byte-
(Continued)
FIGURE 1-5 Receive FIFO
7
ordering capability for compatibility with National Intel or
Motorola microprocessors respectively by selecting the
proper level on the BMODE pin The byte ordering is depict-
ed as follows
Little Endian mode (BMODE
received and transmitted data in the Receive Buffer Area
(RBA) and Transmit Buffer Area (TBA) of system memory is
as follows
Big Endian mode (BMODE
received and transmitted data in the RBA and TBA is as
follows
15
15
Byte 1
Byte 0
MSB
LSB
8
8
16-Bit Word
16-Bit Word
e
e
1) The byte orientation for
0) The byte orientation for
7
7
Byte 0
Byte 1
MSB
LSB
TL F 11722 – 6
0
0