SAB82532H10V32A Infineon Technologies, SAB82532H10V32A Datasheet - Page 135

• Manufacturer Part Number: SAB82532H10V32A
• Description: IC CONTROLLER 2-CH SER 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB82532H10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAB82532H10V32A; SAB82532H10V32AIN

Channel Configuration Register 1 (CCR1)
Access: read/write
Value after RESET: 00
SFLG …
GALP …
GLP …
Semiconductor Group
CCR1
SFLG
7
Enable Shared Flags
If this bit is set, the closing FLAG of a preceding frame
simultaneously becomes the opening FLAG of the following
frame.
Go Active On Loop
Only used if SDLC Loop is enabled.
This bit enables transmission on an SDLC Loop.
1 … After detection of the next EOP sequence, the ESCC2 goes
0 … The ESCC2 leaves the Sending On Loop state when the
Go On Loop
Only used if SDLC Loop is enabled.
This command controls entering and leaving the SDLC Loop.
1 … The ESCC2 enters the On Loop state after detection of the
0 … The ESCC2 leaves the On Loop state by suppressing the
H
to the Sending On Loop state by changing the seventh ‘1’-bit
of the EOP sequence into a ‘0’, thus creating a Start Flag,
and by disconnecting the TxD pin from the RxD pin. The
ESCC2 is now active on loop and can transmit frames as
soon as data is available in the XFIFO. The time between
frames is always filled by sending continuous Flags
(independent from the value of bit CCR1:ITF), thus
occupying the loop.
XFIFO is empty by retransmitting data received on RxD to
TxD (with one bit delay) after the closing flag has been
transmitted (thus creating an EOP sequence).
next EOP sequence by adding a ‘1’-bit delay between
receive and transmit path. The On Loop state is prerequisite
for sending frames on loop.
‘1’-bit delay after detection of the next EOP sequence.
GALP
address: ch-A: 2D
GLP
ch-B: 6D
135
ODS
H
H
ITF/
OIN
Detailed Register Description
SAB 82532/SAF 82532
CM2
CM1
HDLC Mode
CM0
07.96
0