SAB82532H10V32A Infineon Technologies, SAB82532H10V32A Datasheet - Page 152

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SAB82532H10V32A

Manufacturer Part Number
SAB82532H10V32A
Description
IC CONTROLLER 2-CH SER 80-MQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAB82532H10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-SQFP
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAB82532H10V32A
SAB82532H10V32AIN

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
SAB82532H10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Semiconductor Group
AOLP/ALLS …
TIN …
XDU/EXE …
Active On Loop
Only valid if SDLC Loop mode is selected.
It is set in response to a Go Active On Loop command, but not
before an EOP sequence has been received. TxD is disconnected
from RxD and transmission of flags or data is started.
All Sent
Only valid if SDLC loop mode is not selected.
This bit is set
– if the last bit of the current frame is completely sent out on TxD
– if an I-frame is completely sent out on TxD and a positive
– In auto-mode, if an I-frame has been sent and a timer interrupt
Transmit Data Underrun/Extended Transmission End
Transmitted frame was terminated with an abort sequence
because no data was available for transmission in XFIFO and no
XME was issued (interrupt mode) or DMA request was not
satisfied in time (DMA mode).
Note: Transmitter and XFIFO are reset and deactivated if this
In
transmission-end condition (EXE).
Timer Interrupt
The internal timer and repeat counter has expired (see also
description of TIMR register).
and XFIFO is empty (non-auto mode, transparent modes),
acknowledgement has been received (auto mode),
(TIN) is generated because the internal timer expires before an
acknowledgement is received: in this case ALLS is generated
one clock period after (TIN).
extended
condition occurs. They are reactivated not before this
interrupt status register has been read. Thus, XDU should
not be masked via register IMR1.
transparent
152
mode,
Detailed Register Description
SAB 82532/SAF 82532
this
bit
indicates
HDLC Mode
07.96
the

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