SAB82532H10V32A Infineon Technologies, SAB82532H10V32A Datasheet - Page 234

• Manufacturer Part Number: SAB82532H10V32A
• Description: IC CONTROLLER 2-CH SER 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB82532H10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAB82532H10V32A; SAB82532H10V32AIN

Semiconductor Group
Port Interrupt Status Register (PIS)
Access: read
PIS is accessible via both channel addresses (3D
Each of the above bits is assigned to the Universal Port pin (P0 … P7) with the same
number. Bit PISn is set and an interrupt is generated on INT if
– the corresponding Universal Port pin Pn is defined as input via register PCR and
– the interrupt source is enabled by resetting the corresponding interrupt mask PIMn in
– a state transition has occurred on pin Pn. For definite detection of a real state
Note: Bits PISn are reset when register PIS is read. Masked interrupts are not normally
register PIM and
transition, pulse width should not be shorter than 20 ns.
indicated when PIS is read. Instead, they remain internally stored and pending. A
pending interrupt is generated when the corresponding mask bit is reset to ‘zero’.
However, if bit IPC:VIS is set to ‘1’, interrupt statuses in PIS may be flagged
although they are masked via register PIM. These masked interrupt statuses
neither generate an interrupt vector or a signal on INT, nor are visible in register
GIS.
If more than one consecutive state transition occurs on the same pin before the
PIS register is read, only one interrupt request will be generated.
PIS
PIS7
7
address: ch-A: 3D
ch-B: 7D
234
H
H
H
or 7D
Detailed Register Description
H
).
SAB 82532/SAF 82532
BISYNC Mode
PIS0
07.96
0