SAB82532H10V32A Infineon Technologies, SAB82532H10V32A Datasheet - Page 45

• Manufacturer Part Number: SAB82532H10V32A
• Description: IC CONTROLLER 2-CH SER 80-MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB82532H10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAB82532H10V32A; SAB82532H10V32AIN

Each interrupt indication of registers ISR0, ISR1 and PIS can be selectively masked by
setting the corresponding bit in the corresponding mask registers IMR0, IMR1 and PIM.
Use of these registers depends on the selected serial mode. GIS, the non-maskable
Global Interrupt Status Register serves as pointer to pending channel related interrupts
and universal port interrupts.
Interrupt Polling
After ESCC2 has requested an interrupt by activating its INT pin, the CPU must first read
the Global Interrupt Status Register GIS to identify registers with active interrupt
indications. Reading these registers will reset all activated bits and the corresponding
indication in GIS. If all interrupts are acknowledged (GIS is reset), pin INT goes inactive.
Vectorized Interrupt Structure
After ESCC2 has requested an interrupt by activating its INT pin, the system (CPU or
peripherals) starts the interrupt acknowledge cycle by activating the INTA signal. If the
Intel bus interface mode is selected, the two-pulse ’86 mode is supported. In Motorola
interface mode single pulse acknowledgement is implemented.
Interrupt acknowledge operation is determined by the selected interrupt cascading mode
(IPC register) in conjunction with the Interrupt Enable Signals IE0 and IE1 (refer to
chapter 1.3, 1.6, and 10):
– Slave Mode
– Daisy Chaining Mode
If interrupt acknowledge is accepted in one of the above modes, the ESCC2 generates
an interrupt vector which is output on D0-D7 of the data bus independent of the selected
bus interface mode. All interrupt sources are organized in 8 groups with fixed priority
(refer to figure 20).
Semiconductor Group
The address of the slave under service has to be provided via inputs IE0 and IE1
during the valid INTA cycle. Interrupt acknowledge is accepted if this address
corresponds to the programmed value (IPC register).
If the ESCC2 is used in single device applications (no other device is present for
interrupt cascading), IE0 and IE1 have to be fixed to a defined level corresponding to
the internally programmed address.
IE0 as Interrupt Enable Output and IE1 as Interrupt Enable Input are used to build a
Daisy Chain (refer to chapter 1.6). Interrupt acknowledge is accepted if IE1 is active
during the valid INTA cycle. Output IE0 follows the IE1 input. Additionally, IE0 is reset
when INT goes active. During INTA cycles activation of pin INT is prohibited.
45
Microprocessor Interface
SAB 82532/SAF 82532
07.96