AD9910BSVZ Analog Devices Inc, AD9910BSVZ Datasheet - Page 7

• Manufacturer Part Number: AD9910BSVZ
• Description: IC DDS 1GSPS 14BIT PAR 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9910BSVZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Resolution (bits): 14 b
• Master Fclk: 1GHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Pll Type: Frequency Synthesis
• Frequency: 1GHz
• Supply Current: 29mA
• Supply Voltage Range: 1.71V To 1.89V
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9910/PCBZ - BOARD EVAL FOR AD9910 1GSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
SERIAL PORT TIMING CHARACTERISTICS
I/O_UPDATE/PROFILE[2:0] TIMING
TxENABLE and 16-BIT PARALLEL (DATA) BUS TIMING
MISCELLANEOUS TIMING CHARACTERISTICS
DATA LATENCY (PIPELINE DELAY)
CHARACTERISTICS
Minimum Reset Pulse Width High
Data Latency, Single Tone or Using Profiles
Data Latency Using RAM Mode
Data Latency, Sweep Mode
Data Latency, 16-Bit Input Modulation Mode
Maximum SCLK Frequency
Minimum SCLK Clock Pulse Width
Maximum SCLK Rise/Fall Time
Minimum Data Setup Time to SCLK
Minimum Data Hold Time to SCLK
Maximum Data Valid Time in Read Mode
Minimum Setup Time to SYNC_CLK
Minimum Hold Time to SYNC_CLK
I/O_UPDATE Pulse Width
Minimum Profile Toggle Period
Maximum PDCLK Frequency
TxENABLE/Data Setup Time (to PDCLK)
TxENABLE/Data Hold Time (to PDCLK)
Wake-Up Time
201.1 MHz Analog Output
301.1 MHz Analog Output
401.3 MHz Analog Output
Frequency, Phase, Amplitude-to-DAC Output
Frequency, Phase-to-DAC Output
Amplitude-to-DAC Output
Frequency, Phase-to-DAC Output
Amplitude-to-DAC Output
Frequency, Phase-to-DAC Output
Amplitude-to-DAC Output
Frequency, Phase-to-DAC Output
Fast Recovery
Full Sleep Mode
2
Conditions/Comments
±500 kHz
±125 kHz
±12.5 kHz
±500 kHz
±125 kHz
±12.5 kHz
±500 kHz
±125 kHz
±12.5 kHz
Low
High
High
REFCLK multiplier enabled
REFCLK multiplier disabled
Matched latency enabled and OSK
enabled
Matched latency enabled and OSK
disabled
Matched latency disabled
Matched latency disabled
Matched latency enabled/disabled
Matched latency enabled
Matched latency disabled
Matched latency enabled/disabled
Matched latency enabled
Matched latency disabled
Matched latency enabled
Matched latency disabled
Rev. C | Page 7 of 64
Min
4
4
5
0
1.75
0
>1
2
1.75
0
Typ
–87
–87
–91
–86
–86
–88
–84
–84
–85
70
2
250
8
1
5
91
79
79
47
94
106
58
91
91
47
103
91
Max
11
150
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Mbps
ns
ns
ns
ns
ns
ns
ns
ns
SYNC_CLK cycle
SYNC_CLK cycles
MHz
SYSCLK cycles
ms
μs
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
ns
ns
AD9910
3
3
3
3
3
3
3
3
3
3
3
3
3
3