DSPIC30F6014A-30I/PT Microchip Technology Inc., DSPIC30F6014A-30I/PT Datasheet - Page 128

• Manufacturer Part Number: DSPIC30F6014A-30I/PT
• Description: DSP, 16-Bit, 144 KB Flash, 8KB RAM, 68 I/O, TQFP-80
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F6011A/6012A/6013A/6014A
18.3.6
When the DCI module is operating as a frame sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is sam-
pled high (see Figure 18-2). The pulse on the COFS
pin resets the frame sync generator logic.
FIGURE 18-2:
FIGURE 18-3:
FIGURE 18-4:
DS70143C-page 126
Note:
SLAVE FRAME SYNC OPERATION
CSDO or CSDI
CSDI or CSDO
CSDI/CSDO
A 5-bit transfer is shown here for illustration purposes. The I
will be system dependent.
BIT_CLK
CSCK
COFS
SYNC
CSCK
FRAME SYNC TIMING, MULTI-CHANNEL MODE
FRAME SYNC TIMING, AC-LINK START OF FRAME
I
2
S INTERFACE FRAME SYNC TIMING
WS
MSB
S12
bit 2
MSB
bit 1
S12
Preliminary
S12
LSb
MSb
Tag
bit 14
In the I
one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or fall-
ing edge on the COFS pin resets the frame sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to pro-
vide the proper frame length when the module is oper-
ating in the Slave mode. Once a valid frame sync pulse
has been sampled by the module on the COFS pin, an
entire data frame transfer will take place. The module
will not respond to further frame sync pulses until the
data frame transfer has completed.
Tag
LSB MSB
bit 13
Tag
2
2
S protocol does not specify word length – this
S mode, a new data word will be transferred
LSB
© 2006 Microchip Technology Inc.
LSB