DSPIC30F6014A-30I/PT Microchip Technology Inc., DSPIC30F6014A-30I/PT Datasheet - Page 232

• Manufacturer Part Number: DSPIC30F6014A-30I/PT
• Description: DSP, 16-Bit, 144 KB Flash, 8KB RAM, 68 I/O, TQFP-80
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6014A-30I/PT

• A/d Inputs: 16-Channels, 12-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F6011A/6012A/6013A/6014A
O
OC/PWM Module Timing Characteristics.......................... 195
Operating Current (I
Oscillator
Oscillator Configurations ................................................... 146
Oscillator Selection ........................................................... 143
Oscillator Start-up Timer
Output Compare Interrupts ................................................. 89
Output Compare Module..................................................... 87
Output Compare Operation During CPU Idle Mode............ 89
Output Compare Sleep Mode Operation............................. 89
P
Packaging Information ...................................................... 215
Peripheral Module Disable (PMD) Registers .................... 160
PICSTART Plus Development Programmer ..................... 174
Pinout Descriptions ............................................................. 12
POR. See Power-on Reset.
PORTA
PORTB
PORTC
PORTD
PORTF
PORTG
Power Saving Modes
Power-Down Current (I
Power-on Reset (POR) ..................................................... 143
Power-Saving Modes ........................................................ 158
Power-Saving Modes (Sleep and Idle).............................. 143
Power-up Timer
Program Address Space ..................................................... 25
DS70143C-page 230
Control Registers ...................................................... 149
Operating Modes (Table) .......................................... 144
System Overview ...................................................... 143
Fail-Safe Clock Monitor............................................. 148
Fast RC (FRC) .......................................................... 147
Initial Clock Source Selection ................................... 146
Low-Power RC (LPRC) ............................................. 148
LP Oscillator Control ................................................. 147
Phase Locked Loop (PLL) ........................................ 147
Start-up Timer (OST) ................................................ 147
Timing Characteristics .............................................. 189
Timing Requirements ................................................ 190
Register Map............................................................... 90
Timing Characteristics .............................................. 194
Timing Requirements ................................................ 194
Marking ..................................................................... 215
Register Map for dsPIC30F6013A/6014A................... 65
Register Map for dsPIC30F6011A/6012A/
Register Map for dsPIC30F6011A/6012A................... 65
Register Map for dsPIC30F6013A/6014A................... 65
Register Map for dsPIC30F6011A/6012A................... 66
Register Map for dsPIC30F6013A/6014A................... 66
Register Map for dsPIC30F6011A/6012A................... 66
Register Map for dsPIC30F6013A/6014A................... 66
Register Map for dsPIC30F6011A/6012A/
Idle ............................................................................ 159
Sleep ......................................................................... 158
Oscillator Start-up Timer (OST) ................................ 143
Power-up Timer (PWRT) .......................................... 143
Timing Characteristics .............................................. 189
Timing Requirements ................................................ 190
Construction ................................................................ 27
6013A/6014A ...................................................... 65
6013A/6014A ...................................................... 66
DD
)..................................................... 177
PD
) ................................................ 179
Preliminary
Program and EEPROM Characteristics............................ 183
Program Counter ................................................................ 16
Programmable .................................................................. 143
Programmer’s Model .......................................................... 16
Programming Operations.................................................... 53
Protection Against Accidental Writes to OSCCON ........... 149
R
Reader Response............................................................. 234
Reset ........................................................................ 143, 153
Reset Sequence ................................................................. 47
Reset Sources
Reset Timing Characteristics............................................ 189
Reset Timing Requirements ............................................. 190
Resets
RTSP Operation ................................................................. 52
Run-Time Self-Programming (RTSP) ................................. 51
S
Serial Peripheral Interface. See SPI
Simple Capture Event Mode............................................... 83
Simple OC/PWM Mode Timing Requirements ................. 195
Simple Output Compare Match Mode ................................ 88
Simple PWM Mode ............................................................. 88
Software Simulator (MPLAB SIM) .................................... 172
Software Stack Pointer, Frame Pointer .............................. 16
Data Access from Program Memory Using
Data Access from Program Memory Using Table
Data Access from, Address Generation ..................... 27
Data Space Window into Operation............................ 30
Data Table Access (Least Significant Word) .............. 28
Data Table Access (MSB) .......................................... 29
Memory Map for dsPIC30F6011A/6013A................... 26
Memory Map for dsPIC30F6012A/6014A................... 26
Table Instructions
Diagram ...................................................................... 17
Algorithm for Program Flash....................................... 53
Erasing a Row of Program Memory............................ 53
Initiating the Programming Sequence......................... 54
Loading Write Latches ................................................ 54
Reset Sources ............................................................ 47
Brown-out Reset (BOR).............................................. 47
Illegal Instruction Trap ................................................ 47
Trap Lockout............................................................... 47
Uninitialized W Register Trap ..................................... 47
Watchdog Time-out .................................................... 47
Brown-out Rest (BOR), Programmable .................... 155
POR with Long Crystal Start-up Time....................... 155
POR, Operating without FSCM and PWRT .............. 155
Power-on Reset (POR)............................................. 154
Buffer Operation ......................................................... 84
Hall Sensor Mode ....................................................... 84
Prescaler .................................................................... 83
Timer2 and Timer3 Selection Mode............................ 84
Input Pin Fault Protection ........................................... 88
Period ......................................................................... 89
CALL Stack Frame ..................................................... 35
Program Space Visibility..................................... 29
Instructions ......................................................... 28
TBLRDH ............................................................. 28
TBLRDL.............................................................. 28
TBLWTH............................................................. 28
TBLWTL ............................................................. 28
© 2006 Microchip Technology Inc.