DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 127

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A
3C
3D
4C
4D
5C
5D
6C
34
35
36
37
38
39
3A
3B
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
DDR
TR.RSINFO1
TR.RSINFO2
TR.RSINFO3
TR.RSINFO4
TR.RSCSE1
TR.RSCSE2
TR.RSCSE3
TR.RSCSE4
TR.PCVCR1
TR.PCVCR2
TR.FOSCR1
TR.FOSCR2
TR.E1RCR2
TR.E1TCR1
TR.E1TCR2
TR.LCVCR1
TR.LCVCR2
TR.ERCNT
TR.EBCR1
TR.EBCR2
TR.PCLR1
TR.PCLR2
TR.PCLR3
TR.PCLR4
TR.SIGCR
TR.BOCC
TR.ESCR
TR.LBCR
TR.RS10
TR.RS11
TR.RS12
TR.RS13
TR.TS10
TR.TS11
TR.TS12
TR.TS13
TR.TS14
TR.TS15
TR.TS16
TR.RS1
TR.RS2
TR.RS3
TR.RS4
TR.RS5
TR.RS6
TR.RS7
TR.RS8
TR.RS9
TR.TS1
TR.TS2
TR.TS3
TR.TS4
TR.TS5
TR.TS6
TR.TS7
TR.TS8
TR.TS9
N
AME
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Transmit Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
Receive Signaling Bit Format Changes With Operating Mode. See Register Definition.
PCVC15
TESALGN
LCVC15
GRSRE
Reserved
PCVC7
LCVC7
FOS15
FOS7
TFPT
CH16
CH24
CH16
CH24
CH16
CH24
CH32
EB15
B
CH8
CH8
CH8
EB7
LTS
—
—
—
—
—
IT
7
PCVC14
LCVC14
Reserved
PCVC6
LCVC6
FOS14
MECU
TESR
CH15
CH23
CH15
CH23
FOS6
CH15
CH23
CH31
T16S
EB14
B
CH7
CH7
EB6
CH7
—-
—
—
—
—
—
IT
6
TESMDM
PCVC13
LCVC13
Reserved
PCVC5
LCVC5
FOS13
ECUS
FOS5
TUA1
CH14
CH22
CH30
CH14
CH22
CH30
CH14
CH22
CH30
EB13
B
CH6
CH6
CH6
EB5
—
—
—
—
IT
5
127 of 335
Reserved
PCVC12
LCVC12
RBOCE
Reserved
PCVC4
LCVC4
FOS12
EAMS
CH21
CH29
FOS4
TESE
CH13
CH13
CH21
CH29
EB12
CH13
CH21
CH29
B
TSiS
CH5
CH5
RFE
CH5
EB4
—
IT
4
RESALGN
LCVC11
PCVC11
Reserved
VCRFS
PCVC3
LCVC3
FOS11
TSA1
CH12
CH20
CH28
CH12
CH20
CH28
FOS3
CH12
CH20
CH28
EB11
B
RBR
CH4
CH4
RFF
EB3
CH4
LLB
—
IT
3
PCVC10
LCVC10
THDB3
PCVC2
LCVC2
FOS10
RCCS
RESR
AEBE
RBF1
CH11
CH19
CH27
CH11
CH19
CH27
FSBE
FOS2
CH11
CH19
CH27
EB10
B
CH3
CH3
EB2
RLB
CH3
—
IT
2
MOSCRF
RESMDM
PCVC9
PCVC1
LCVC9
LCVC1
TG802
TCCS
FOS9
FOS1
RBF0
CH10
CH18
CH26
CH10
CH18
CH26
CH10
CH18
CH26
AAIS
B
CH2
CH2
CH2
EB9
EB1
PLB
—
IT
1
LCVCRF
FRSAO
TCRC4
PCVC8
PCVC0
LCCV8
LCVC0
SBOC
RCLA
RESE
CH17
CH25
CH17
CH25
FOS8
FOS0
CH17
CH25
B
ARA
CH1
CH9
CH1
CH9
CH1
CH9
EB8
EB0
FLB
IT
0