DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 55

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Frames with errors are usually rejected by the device. The user has the option of accepting frames by settings in
Receive Frame Rejection Control register (SU.RFRC). The user can program whether to reject or accept frames
with the following errors:
Note that frames received that are runt frames or frames with collision will automatically be rejected.
Table 9-7. Registers Related to the Ethernet Port
Transmit Frame Resend Control
Transmit Frame Status Low and
Transmit Frame Status High
Receive Frame Status Byte 0 to 3
Receive Frame Rejection Control
Receiver Maximum Frame High
Register and Receiver Maximum
Frame Low Register
MAC Control Register
•
•
•
•
•
•
MII error asserted during the reception of the frame
Dribbling bits occurred in the frame
CRC error occurred
Length error occurred—the length indicated by the frame length is inconsistent with the number of bytes
received
Control frame was received. The mode must be full duplex
Unsupported control frame was received
REGISTER
SU.RFSB0
SU.TFSL
SU.RMFSRH
SU.RMFSRL
SU.MACCR
SU.RFRC
SU.TFRC
NAME
and
to
55 of 335
SU.RFSB3
SU.TFSH
and
This register determines if the current frame is
retransmitted due to various transmit errors.
These 2 registers provide the real time status
of the transmit frame. Only apply to the last
frame transmitted.
These registers provide the real time status
for the received frame. Only apply to the last
frame received.
This register provides settings for reception or
rejection of frame based on errors detected
by the MAC.
The settings for this register provide the
maximum size of frames to be accepted from
the MII/RMII receive interface.
This register provides configuration control for
the MAC.
FUNCTION