DS33R41+ Maxim Integrated Products, DS33R41+ Datasheet - Page 7

• Manufacturer Part Number: DS33R41+
• Description: IC TXRX ETHERNET MAP 400-BGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS33R41+

• Number Of Drivers/receivers: 4/4
• Protocol: T1/E1/J1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
Figure 13-22. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled) .............................304
Figure 13-23. Transmit IBO Channel Interleave Mode Timing..........................................................................................304
Figure 14-1. Transmit MII Interface Timing .......................................................................................................................307
Figure 14-2. Receive MII Interface Timing ........................................................................................................................308
Figure 14-3. Transmit RMII Interface Timing.....................................................................................................................309
Figure 14-4. Receive RMII Interface Timing......................................................................................................................310
Figure 14-5. MDIO Interface Timing..................................................................................................................................311
Figure 14-6. Transmit WAN Timing...................................................................................................................................312
Figure 14-7. Receive WAN Timing ....................................................................................................................................313
Figure 14-8. SDRAM Interface Timing ..............................................................................................................................315
Figure 14-9. Intel Bus Read Timing (MODEC = 00)..........................................................................................................317
Figure 14-10. Intel Bus Write Timing (MODEC = 00) ........................................................................................................317
Figure 14-11. Motorola Bus Read Timing (MODEC = 01).................................................................................................318
Figure 14-12. Motorola Bus Write Timing (MODEC = 01).................................................................................................318
Figure 14-13. JTAG Interface Timing ................................................................................................................................319
Figure 14-14. Receive Side Timing, Elastic Store Disabled (T1 Mode) ............................................................................321
Figure 14-15. Receive Side Timing, Elastic Store Disabled (E1 Mode) ............................................................................322
Figure 14-16. Receive Side Timing, Elastic Store Enabled (T1 Mode) .............................................................................322
Figure 14-17. Receive Side Timing, Elastic Store Enabled (E1 Mode) .............................................................................323
Figure 14-18. Receive Line Interface Timing ....................................................................................................................323
Figure 14-19. Transmit Side Timing, Elastic Store Disabled .............................................................................................325
Figure 14-20. Transmit Side Timing, Elastic Store Enabled..............................................................................................326
Figure 14-21. Transmit Line Interface Timing ...................................................................................................................326
Figure 15-1. JTAG Functional Block Diagram ...................................................................................................................327
Figure 15-2. TAP Controller State Diagram ......................................................................................................................330
Figure 15-3. JTAG Functional Timing ...............................................................................................................................333
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