PIC12F509-I/P Microchip Technology Inc., PIC12F509-I/P Datasheet - Page 48

• Manufacturer Part Number: PIC12F509-I/P
• Description: 8 PIN, 1.5 KB FLASH, 41 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F509-I/P

• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 4 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 41 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F508/509/16F505
7.3.2
This configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
FIGURE 7-7:
7.4
The PIC12F508/509/16F505 devices incorporate an
on-chip Power-on Reset (POR) circuitry, which
provides an internal chip Reset for most power-up
situations.
The on-chip POR circuit holds the chip in Reset until
V
ation. To take advantage of the internal POR, program
the (GP3/RB3)/MCLR/V
through a resistor to V
RB3). An internal weak pull-up resistor is implemented
using a transistor (refer to Table 10-2 for the pull-up
resistor ranges). This will eliminate external RC compo-
nents usually needed to create a Power-on Reset. A
maximum rise time for V
Section 10.0 “Electrical Characteristics” for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 7-8.
DS41236B-page 46
MCLRE
DD
DD
GPWU/RBWU
and the pin is assigned to be a I/O. See Figure 7-7.
has reached a high enough level for proper oper-
Power-on Reset (POR)
MCLR ENABLE
DD
MCLR SELECT
, or program the pin as (GP3/
PP
pin as MCLR and tie
DD
(GP3/RB3)/MCLR/V
is specified. See
Internal MCLR
PP
Preliminary
The Power-on Reset circuit and the Device Reset
Timer (see Section 7.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 18 ms, it will reset the
Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 7-9. V
bringing MCLR high. The chip will actually come out of
Reset T
In Figure 7-10, the on-chip Power-on Reset feature is
being used (MCLR and V
is programmed to be (GP3/RB3). The V
before the start-up timer times out and there is no prob-
lem in getting a proper Reset. However, Figure 7-11
depicts a problem situation where V
The time between when the DRT senses that MCLR is
high and when MCLR and V
value, is too long. In this situation, when the start-up
timer times out, V
value and the chip may not function correctly. For such
situations, we recommend that external RC circuits be
used to achieve longer POR delay times (Figure 7-10).
For additional information, refer to Application Notes
AN522 “Power-Up Considerations” (DS00522) and
AN607 “Power-up Trouble Shooting” (DS00607).
Note:
DRT
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
msec after MCLR goes high.
DD
is allowed to rise and stabilize before
DD
has not reached the V
© 2005 Microchip Technology Inc.
DD
are tied together or the pin
DD
actually reach their full
DD
rises too slowly.
DD
is stable
DD
(min)