PIC12F509-I/P Microchip Technology Inc., PIC12F509-I/P Datasheet - Page 51

• Manufacturer Part Number: PIC12F509-I/P
• Description: 8 PIN, 1.5 KB FLASH, 41 RAM, 6 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC12F509-I/P

• Cpu Speed: 1 MIPS
• Eeprom Memory: 0 Bytes
• Frequency: 4 MHz
• Input Output: 6
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 8-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 41 Bytes
• Speed: 4 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.5
On the PIC12F508/509/16F505 devices, the DRT runs
any time the device is powered up. DRT runs from
Reset and varies based on oscillator selection and
Reset type (see Table 7-6).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition for approximately 18 ms after MCLR
has
Programming (GP3/RB3)/MCLR/V
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications, as
well as allowing the use of the (GP3/RB3)/MCLR/V
pin as a general purpose input.
The Device Reset Time delays will vary from chip-to-
chip due to V
See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 7.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
7.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 7.1
“Configuration Bits”). Refer to the PIC12F508/509/
16F505 Programming Specifications to determine how
to access the Configuration Word.
© 2005 Microchip Technology Inc.
reached
Device Reset Timer (DRT)
Watchdog Timer (WDT)
DD
a
, temperature and process variation.
logic
DD
high
to rise above V
(V
PP
IH
as MCLR and
MCLR)
DD
min. and
level.
Preliminary
PP
PIC12F508/509/16F505
TABLE 7-6:
7.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These peri-
ods vary with temperature, V
cess variations (see DC specs).
Under worst case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
INTOSC, EXTRC
HS
EC
Note 1:
Configuration
(1)
(1)
Oscillator
, XT, LP
PIC16F505 only.
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
18 ms (typical)
18 ms (typical)
POR Reset
DD
DD
and part-to-part pro-
= Min., Temperature
DS41236B-page 49
18 ms (typical)
10 s (typical)
10 s (typical)
Subsequent
Resets