PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 320

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC24FJ256DA210 FAMILY
REGISTER 22-26: G1CLUTWR: COLOR LOOK-UP TABLE (CLUT) MEMORY WRITE DATA
REGISTER 22-27: G1CLUTRD: COLOR LOOK-UP TABLE (CLUT) MEMORY READ DATA REGISTER
DS39969B-page 320
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
CLUTWR15
CLUTRD15
CLUTWR7
CLUTRD7
R-0, HSC
R-0, HSC
R/W-0
R/W-0
CLUTRD<15:0>: Color Look-up Table Memory Read Data bits
This register contains the most recent read from the CLUT memory pointed to by the CLUTADR bits
(G1CLUT<7:0>). Reading of the CLUT memory is triggered when the CLUTTRD bit (G1CLUT<9>) goes
from ‘0’ to ‘1’. Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module
(GFX)” for details on reading entries from the CLUT.
CLUTWR<15:0>: Color Look-up Table Memory Write Data bits
A write to this register triggers a write to the CLUT memory at the address pointed to by the CLUTADR
bits. A word write or a high byte write to this register triggers a write to the CLUT memory at the address
pointed to by CLUTADR. Low byte write to this register will only update the G1CLUTWR<7:0> and no
write to CLUT memory will be triggered. During power-up and power-down of the display, the most
recent data written to this register will be used to control the timing of the GPWR signal. Refer to the
“PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details on
writing entries to the CLUT.
CLUTWR14
CLUTRD14
CLUTWR6
CLUTRD6
R-0, HSC
R-0, HSC
R/W-0
R/W-0
REGISTER
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
CLUTRD13
CLUTWR13
CLUTRD5
CLUTWR5
R-0, HSC
R-0, HSC
R/W-0
R/W-0
CLUTRD12
CLUTRD4
R-0, HSC
R-0, HSC
CLUTWR12
CLUTWR4
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CLUTRD11
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CLUTRD3
R-0, HSC
R-0, HSC
CLUTWR11
CLUTWR3
R/W-0
R/W-0
CLUTRD10
CLUTWR10
CLUTRD2
CLUTWR2
R-0, HSC
R-0, HSC
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
CLUTWR9
CLUTWR1
CLUTRD9
CLUTRD1
R-0, HSC
R-0, HSC
R/W-0
R/W-0
CLUTRD8
CLUTWR8
CLUTWR0
R-0, HSC
CLUTRD0
R-0, HSC
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0