PIC24FJ256DA210-I/PT Microchip Technology Inc., PIC24FJ256DA210-I/PT Datasheet - Page 77

• Manufacturer Part Number: PIC24FJ256DA210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB, Graphics
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256DA210-I/PT

• A/d Inputs: 24 Channel, 10-Bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART
• Memory Capacity: 256 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Leads: 100
• Number Of Pins: 100
• Package Type: 100-Pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 96K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to +85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Voltage, Rating: 2.2-3.6 V
• Run Mode: 800 μA/MIPS, 3.3 V Typical
• Standby Current With 32 Khz Oscillator: 22 μA, 3.3 V Typical
• Lead Free Status / Rohs Status: RoHS Compliant part

4.3.2
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
data space. The TBLRDH and TBLWTH instructions are
the only method to read or write the upper 8 bits of a
program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
FIGURE 4-9:
 2010 Microchip Technology Inc.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
TBLPAG
02
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
23
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
15
0
000000h
020000h
030000h
800000h
PIC24FJ256DA210 FAMILY
Program Space
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
2.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are described in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address register (TBLPAG). TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG<7> = 0, the table page is located in the user
memory space. When TBLPAG<7> = 1, the page is
located in configuration space.
Note:
‘Phantom’ Byte
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom’ byte, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (byte select = 1).
00000000
00000000
00000000
00000000
Only table read operations will execute in
the configuration memory space, where
Device IDs are located. Table write
operations are not allowed.
23
16
Data EA<15:0>
DS39969B-page 77
8
0