ICS1893CY-10LFT IDT, Integrated Device Technology Inc, ICS1893CY-10LFT Datasheet
ICS1893CY-10LFT
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ICS1893CY-10LFT Summary of contents
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... Carrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893CY-10 supports managed or unmanaged node, repeater, and switch applications. The ICS1893CY-10 is intended for MII, Node applications that require the Auto-MIDIX feature that automatically corrects crossover errors in plant wiring. The ICS1893CY-10 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer ...
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... ICS1893CY-10 Data Sheet - Release Section Revision History ............................................................................................................................. 9 Chapter 1 Abbreviations and Acronyms ......................................................................................... 10 Chapter 2 Conventions and Nomenclature..................................................................................... 12 Chapter 3 Overview of the ICS1893CY-10 ....................................................................................... 14 3.1 100Base-TX Operation ..........................................................................................15 3.2 10Base-T Operation ...............................................................................................15 Chapter 4 Operating Modes Overview............................................................................................. 16 4.1 Reset Operations ...................................................................................................17 4.1.1 General Reset Operations .....................................................................................17 4.1.2 Specific Reset Operations .....................................................................................18 4.2 Power-Down Operations ...
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... Operation: Auto Polarity Correction .......................................................52 6.5.14 10Base-T Operation: Isolation Transformer ...........................................................52 6.6 Functional Block: Management Interface ...............................................................53 6.6.1 Management Register Set Summary .....................................................................53 6.6.2 Management Frame Structure ...............................................................................53 ICS1893CY-10 Rev 1/07 Table of Contents Title Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 3 Table of Contents Page ...
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... ICS1893CY-10 Data Sheet - Release Section Chapter 7 Management Register Set ............................................................................................... 56 7.1 Introduction to Management Register Set .............................................................57 7.1.1 Management Register Set Outline .........................................................................57 7.1.2 Management Register Bit Access ..........................................................................58 7.1.3 Management Register Bit Default Values ..............................................................58 7.1.4 Management Register Bit Special Functions .........................................................59 7.2 Register 0: Control Register ...................................................................................60 7.2.1 Reset (bit 0 ...
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... IEEE Reserved Bit (bit 8.14) ..................................................................................83 7.10.3 Message Page (bit 8.13) ........................................................................................83 7.10.4 Acknowledge 2 (bit 8.12) .......................................................................................83 7.10.5 Message Code Field / Unformatted Code Field (bits 8.10:0) .................................83 ICS1893CY-10 Rev 1/07 Table of Contents Title Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 5 Table of Contents ...
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... ICS1893CY-10 Data Sheet - Release Section 7.11 Register 16: Extended Control Register ................................................................84 7.11.1 Command Override Write Enable (bit 16.15) .........................................................85 7.11.2 ICS Reserved (bits 16.14:11) .................................................................................85 7.11.3 PHY Address (bits 16.10:6) ...................................................................................85 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) .....................................................85 7.11.5 ICS Reserved (bit 16.4) .........................................................................................85 7.11.6 NRZ/NRZI Encoding (bit 16 ...
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... Automatic 100Base-TX Power-Down (bit 19.0) .....................................................97 Chapter 8 Pin Diagram, Listings, and Descriptions ....................................................................... 98 8.1 ICS1893CY-10 Pin Diagram ..................................................................................98 8.2 ICS1893CY-10 Pin Listings ....................................................................................99 8.3 ICS1893CY-10 Pin Descriptions ..........................................................................100 8.3.1 Transformer Interface Pins ..................................................................................100 8.3.2 Multi-Function (Multiplexed) Pins: PHY Address and LED Pins ..........................101 8.3.3 Configuration Pins ................................................................................................104 8.3.4 MAC/Repeater Interface Pins ...
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... Jabber Timing .....................................................................................138 9.5.21 10Base-T: Normal Link Pulse Timing ..................................................................139 9.5.22 Auto-Negotiation Fast Link Pulse Timing .............................................................140 Chapter 10 Physical Dimensions of ICS1893CY-10 Package...................................................... 141 Chapter 11 Ordering Information..................................................................................................... 142 ICS1893CY-10 Rev 1/07 Table of Contents Title Copyright © 2007, Integrated Device Technology, Inc. ...
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... ICS1893CY-10 - Release Revision History • The initial release of this document, Rev A, is dated November 2006 • Rev 1/07 - changed resistor values on Figure 9-1. ICS1893CY-10 Rev 1/07 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 9 Revision History ...
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... ICS1893CY-10 Data Sheet - Release Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table 1-1. Abbreviations and Acronyms Abbreviation / Acronym 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor ...
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... ICS1893CY-10 - Release Table 1-1. Abbreviations and Acronyms (Continued) Abbreviation / Acronym OUI Organizationally Unique Identifier PCS Physical Coding sublayer PHY The ICS1893CY- physical-layer device, also referred ‘PHY’ or ‘PHYceiver’. PLL phase-locked loop PMA Physical Medium Attachment PMD Physical Medium Dependent ppm ...
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... All pin or signal names are provided in capital letters. • A pin name that includes a forward slash ‘/’ multi-function, configuration pin. These pins provide the ability to select between two ICS1893CY-10 functions. The name provided: – Before the ‘/’ indicates the pin name and function when the signal level on the pin is logic zero. – ...
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... In reference to the ICS1893CY-10, the term ‘Twisted-Pair Receiver’ refers to the set of Twisted-Pair Receive output pins (TP_RXP and TP_RXN). In reference to the ICS1893CY-10, the term ‘Twisted-Pair Transmitter’ refers to the set of Twisted-Pair Transmit output pins (TP_TXP and TP_TXN). Copyright © 2007, Integrated Device Technology, Inc. ...
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... Auto-Negotiation sublayer The ICS1893CY-10 is transparent to the next layer of the OSI model, the link layer. The link layer has two sublayers: the Logical Link Control sublayer and the MAC sublayer. The ICS1893CY-10 can interface directly to the MAC and offers multiple, configurable modes of operation. Alternately, this configurable interface can be connected to a repeater, which extends the physical layer of the OSI model ...
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... When receiving data from the medium, the ICS1893CY-10 removes each SSD and replaces it with the pre-defined preamble pattern before presenting the nibbles to its MAC/Repeater Interface. When the ICS1893CY-10 encounters an ESD in the received data stream, signifying the end of the frame, it ends the presentation of nibbles to its MAC/Repeater Interface. Therefore, the local MAC/repeater receives an unaltered copy of the transmitted frame sent by the remote MAC/repeater ...
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... HW/SW (hardware/software) pin determines which method the ICS1893CY- use, either its hardware pins or its register bits. When the HW/SW bit is logic zero the ICS1893CY- hardware mode. In hardware mode, the hardware pins have priority over the internal registers for establishing the configuration settings of the ICS1893CY-10 ...
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... Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition is removed 4.1.1.3 Hot Insertion As with the ICS189X products, the ICS1893CY-10 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1893CY-10 can connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the MAC/repeater.) ICS1893CY-10 Rev 1/07 Operations” ...
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... Section 4.1.1.1, “Entering Exiting Hardware Reset After the signal on the RESETn pin transitions from a low to a high state, the ICS1893CY-10 completes in 640 ns (that is REF_IN clocks) steps 1 through 5, listed in first five steps are completed, the Serial Management Port is ready for normal operations, but this action does not signify the end of the reset cycle ...
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... LL, LH, and LMX Management Register bits are re-initialized to their default values. • During a reset, the ICS1893CY-10 sets all of its Management Register bits to their default values. It does not maintain the state of any Management Register bit. For more information on power-down operations, see the following: • ...
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... For example, if the ICS1893CY-10 supports 100Base-TX and 10Base-T modes – but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select 100Base-TX as the highest-performance common operating mode ...
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... Data conversion from both parallel-to-serial and serial-to-parallel formats • Manchester data encoding/decoding • Data transmission/reception over a twisted-pair medium In addition, in 10Base-T mode, the ICS1893CY-10 provides a variety of control and status means to assist with Link Segment management. For more information on 10Base-T, see 10Base-T Operations”. 4.7 Half-Duplex and Full-Duplex Operations The ICS1893CY-10 supports half-duplex and full-duplex operations for both 10Base-T and 100Base-TX applications ...
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... ICS1893CY-10 Data Sheet - Release 4.8 Auto-MDI/MDIX Crossover (New) The ICS1893CY-10 includes the auto-MDI/MDIX crossover feature typical CAT 5 Ethernet installation the transmit twisted pair signal pins of the RJ45 connector are crossed over in the CAT 5 wiring to the partners receive twisted pair signal pins and receive twisted pair to the partners transmit twisted pair. This is usually accomplished in the wiring plant ...
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... ICS1893CY-10 - Release Chapter 5 Interface Overviews The ICS1893CY-10 MAC/Repeater Interface is fully configurable, thereby allowing it to accommodate many different applications. This chapter includes overviews of the following MAC/repeater-to-PHY interfaces: • Section 5.1, “MII Data Interface” • Section 5.2, “100M Symbol Interface” • ...
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... PHY and the MAC/repeater as framed, 4-bit parallel nibbles. In addition, the interface also provides status and control signals to synchronize the transfers. The ICS1893CY-10 provides a full complement of the ISO/IEC-specified MII signals. Its MII has both a transmit and a receive data path to synchronously exchange 4 bits of data (that is, nibbles). ...
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... In the 100M Symbol Interface mode, the ICS1893CY-10 continues to assert the CRS signal using its PCS logic. This action does not affect the bit delay or latency because the PCS CRS logic examines the bits received from the PMA sublayer serially ...
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... ICS1893CY-10 Data Sheet - Release Table 5-1 lists the pin mappings for the ICS1893CY-10 100M Symbol Interface mode. Table 5-1. Pin Mappings for 100M Symbol Interface Mode Default 10M / 100M MII Pin Names COL No connect. [Because the MAC/repeater sources both active and ‘idle’ data, a PHY cannot distinguish between an active and idle transmission channel (that is PHY the transmit channel always appears active) ...
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... ICS1893CY-10 - Release 5.3 10M Serial Interface When the Mac/Repeater Interface is configured as a 10M Serial Interface, the ICS1893CY-10 and the MAC/repeater exchange a framed, serial bit stream along with associated control signals. The 10M Serial Interface configuration is ideally suited to applications that already incorporate a serial 10Base-T MAC with a standard ‘ ...
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... ICS1893CY-10 Data Sheet - Release Table 5-2 lists the pin mappings for the ICS1893CY-10 10M Serial Interface mode. Table 5-2. Pin Mappings for 10M Serial Interface Mode Default 10M / 100M MII Pin Names COL 10COL CRS 10CRS MDC MDC MDIO MDIO RXCLK ...
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... ICS1893CY-10. The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of Management Registers that provide the STA with access to a PHY such as the ICS1893CY-10. A Serial Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an associated input pin for a clock (MDC) ...
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... ICS1893CY-10 Data Sheet - Release Figure 5-1. ICS1893CY-10 Transmit Twisted Pair * TP_AP 5 ICS1893CY-10 TP_AN 6 Ideally, for these traces Z TP_BP 10 TP_BN 9 Ideally, for these traces Z * For backward compatibility, refer to the the “1893C Alternate Schematic” application note. ICS1893CY-10, Rev. 1/07 System Ground Plane 1:1 49.9Ω ...
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... MHz ±50 parts per million. This accuracy is necessary to meet the interface requirements of the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1 and 24.2.3.4. The ICS1893CY-10 supports two clock source configurations: a CMOS oscillator or a CMOS driver. The input to REF_IN is CMOS (10% to 90% VDD), not TTL. Alternately, a 25MHz crystal may be used. The Oscillator specifications are shown in Table 5 ...
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... If a crystal is used as the clocking source, connect it to both the Ref_in (pin 47) and Ref_out (pin 46) pins of the ICS1893CY-10. A pair of bypass capacitors on either side of the crystal are connected to ground. The crystal is used in the parallel resonance or anti-resonance mode. The value of the bypass caps serve to adjust the final frequency of the crystal oscillation ...
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... Functionally, the RXTRI pin affects the MII receive channel in the same way as the Control Register’s isolate bit, bit 0.10. (The isolate bit also affects the transmit data path.) The ICS1893CY-10 can tri-state these seven signals for all five types of MAC/Repeater Interface configurations, not just the MII interface. ...
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... ICS1893CY-10 Data Sheet - Release 5.8 Status Interface The ICS1893CY-10 LSTA pin provides a Link Status, and its LOCK pin provides a Stream Cipher Locking Status. In addition, as listed in that report the results of continual link monitoring by providing signals that are intended for driving LEDs. (For the pin numbers, see Table Table 5-5 ...
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... ICS1893CY-10 - Release Figure 5-3 shows typical biasing and LED connections for the ICS1893CY-10. Figure 5-3. ICS1893CY-10 LED - PHY Address P4RD P3TD 64 62 REC TRANS 10K Ω 10K Ω This circuit decodes to PHY address = 1. Note: 1. All LED pins must be set during reset. ...
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... ICS1893CY-10 Data Sheet - Release Chapter 6 Functional Blocks This chapter discusses the following ICS1893CY-10 functional blocks. • Section 6.1, “Functional Block: Media Independent Interface” • Section 6.2, “Functional Block: Auto-Negotiation” • Section 6.3, “Functional Block: 100Base-X PCS and PMA Sublayers” ...
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... Functional Block: Media Independent Interface All ICS1893CY-10 MII interface signals are fully compliant with the ISO/IEC 8802-3 standard. In addition, the ICS1893CY-10 MIIs can support two data transfer rates: 25 MHz (for 100Base-TX operations) and 2.5 MHz (for 10Base-T operations). The Media Independent Interface (MII) consists of two primary components: 1 ...
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... The ICS1893CY-10 obtains the data for its FLP bursts from the Auto-Negotiation Advertisement Register (Register 4). 3. Both the ICS1893CY-10 and the remote link partner substitute Fast Link Pulse (FLP) bursts in place of the Normal Link Pulses (NLPs). In each FLP burst, the ICS1893CY-10 transmits information on its technology capability through its Link Control Word, which includes link configuration and status data ...
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... A remote link partner that does not support the auto-negotiation process does not respond to the transmitted FLP bursts. The ICS1893CY-10 detects this situation and responds according to the data it receives. The ICS1893CY-10 can receive one of five potential responses to the FLP bursts it is transmitting: FLP bursts, 10Base-T link pulses (that is, Normal Link Pulses), scrambled 100Base IDLEs, nothing combination of signal types ...
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... Auto-Negotiation: Remote Fault Signaling If the remote link partner detects a fault, the ICS1893CY-10 reports the remotely detected fault to the STA by setting to logic one the Remote Fault Detected bit(s), 1.4, 5.13, 17.1, and 19.13. In general, the reception of a remote fault means that the remote link partner has a problem with the integrity of its receive channel ...
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... STA can determine the cause of the link failure by using the outputs of the ICS1893CY-10 Auto-Negotiation Progress Monitor. The Auto-Negotiation Progress Monitor provides the STA with four status bits of data to indicate both the history and the present state of the auto-negotiation process ...
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... Note: When configured for 100M Symbol mode operations, the MAC/Repeater Interface bypasses most of the PCS. When the ICS1893CY-10 MAC/Repeater Interface is in this mode, most of its PCS Transmit and Receive modules are inactive. However, its PCS control functions (CRS and COL) remain operational. ...
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... Full-duplex mode, COL is always FALSE. 6.3.3.2 PMA Transmit Module The ICS1893CY-10 PMA Transmit module accepts a serial bit stream from its PCS and converts the data into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium Dependent (TP-PMD) sublayer. ...
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... Both the PCS and PMA sublayers have Receive modules. 6.3.4.1 PCS Receive Module The ICS1893CY-10 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and then processes the data to detect the presence of a carrier ...
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... A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6) to logic one. Note: An STA can force the ICS1893CY-10 to transmit symbols that are typically classified as invalid, by both (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic one and (2) asserting the associated TXER signal. For more information, see ...
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... Baseline wander adversely affects the noise immunity of the receiver, because the ‘baseline’ signal moves or ‘wanders’ from its nominal DC value. The ICS1893CY-10 uses a unique technique to restore the DC component ‘lost’ by the medium result, the design is very robust, immune to noise and independent of the data stream ...
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... The DSP-based adaptive equalizer uses a technique that compensates for a wide range of cable lengths. The optimizing parameter for the equalization process is the overall bit error rate of the ICS1893CY-10. This technique closes the loop on the entire data reception process and provides a very high overall reliability. ...
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... Operation: Manchester Encoder/Decoder During data transmission the ICS1893CY-10 acquires data from its MAC/Repeater Interface in either 4-bit nibbles serial bit stream. The ICS1893CY-10 converts this data into a Manchester-encoded signal for presentation to its MDI, as required by the ISO/IEC specification Manchester-encoded signal, all logic: • ...
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... MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the ICS1893CY-10 periodically transmits link pulses at a rate of one link pulse every compliance with the ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1893CY-10 continues transmitting link pulses even while receiving data ...
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... When a link is invalid and the Link Monitor Function detects the presence of data, the ICS1893CY-10 does not transition the link to the valid state until after the reception of the present packet is complete. ...
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... When enabled, the ICS1893CY-10 performs the SQE Test at the completion of each transmitted packet (that is, whenever its TX_EN signal transitions from asserted to de-asserted). When the ICS1893CY-10 executes its SQE Test, it asserts the COL signal to its MAC Interface for a pre-determined time duration (ISO/IEC specified). [For more information, see Heartbeat Timing (SQE)” ...
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... ICS1893CY-10 Data Sheet - Release – The ICS1893CY-10 SQE Test Inhibit bit (bit 18.2) in the 10Base-T Operations Register is logic one. [This bit provides the Station Management entity (STA) with the ability to disable the SQE Test function.] Note 10Base-T mode, a bit time has a typical duration of 100 ns. ...
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... Management Frame Structure The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the exchange of configuration, control, and status data between a PHY, such as an ICS1893CY-10, and an STA. All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange data through a pre-defined register set ...
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... A valid Management Frame includes an operation code (OP) immediately following the start-of-frame delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one for writing to a management register, 01b. The ICS1893CY-10 does not respond to the codes 00b and 11b, which the ISO/IEC specification defines as invalid. ...
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... Read, an ICS1893CY-10 remains in the high-impedance state during the first bit time and subsequently drives its MDIO pin to logic zero for the second bit time. • Write, an ICS1893CY-10 waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin. 6.6.2.8 Management Frame Data A valid management frame includes a 16-bit Data field for exchanging the register contents between the ICS1893CY-10 and the STA ...
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... ICS1893CY-10 Data Sheet - Release Chapter 7 Management Register Set The tables in this chapter detail the functionality of the bits in the management register set. The tables include the register locations, the bit positions, the bit definitions, the STA Read/Write Access Types, the default bit values, and any special bit functions or capabilities (such as self-clearing). Following each table is a description of each bit. This chapter includes the following sections: • ...
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... Reserved by IEEE 16 through 31 Vendor-Specific (ICS) Registers Table 7-2 lists the ICS-specific registers that the ICS1893CY-10 implements. These registers enhance the performance of the ICS1893CY-10 and provide the Station Management entity (STA) with additional control and status capabilities. Table 7-2. ICS-Specific Registers Register Address 16 ...
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... Read/Write Zero R/W0 7.1.3 Management Register Bit Default Values The tables in this chapter specify for each register bit the default value, if one exists. The ICS1893CY-10 sets all Management Register bits to their default values after a reset. for ICS1893CY-10 Management Register bits. Table 7-4. Range of Possible Valid Default Values for ICS1893CY-10 Register Bits Default Condition – ...
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... LMX bits retain their value until either a reset occurs or they are read by an STA. Immediately following an STA read of a defined group of LMX bits, the ICS1893CY-10 latches the current state of the monitored state machine into the LMX bits. When an STA reads a group of LMX bits: • ...
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... Reserved bits. 7.2.1 Reset (bit 0.15) This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893CY-10 software reset during which all Management Registers are set to their default values and all internal state machines are set to their idle state. For a detailed description of the software reset process, see “ ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893CY-10 is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893CY-10 isolates this bit 0.13 and uses the 10/100SEL input pin to establish the data rate for the ICS1893CY-10. In this Hardware mode: – Bit 0.13 is undefined. ...
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... Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893CY-10 isolates itself from the MAC/Repeater Interface. • Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893CY-10 does not isolate its MAC/Repeater Interface. 7.2.7 Restart Auto-Negotiation (bit 0.9) This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is logic one) ...
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... HW/SW input pin and the Auto-Negotiation Enable bit (bit 0.12). When the ICS1893CY-10 is configured for: • Hardware mode (that is, the HW/SW pin is logic zero), the ICS1893CY-10 isolates bit 0.8 and uses the DPXSEL input pin to establish the Duplex mode for the ICS1893CY-10. In this Hardware mode: – Bit 0.8 is undefined. ...
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... Table 7-6 lists the Status Register bits. These 16 bits of data provide an interface between the ICS1893CY-10 and an STA. There are two types of status bits: some report the capabilities of the port, and some indicate the state of signals used to monitor internal circuits. The STA accesses the Status Register using the Serial Management Interface. During a reset, the ICS1893CY-10 initializes the Status Register bits to pre-defined, default values ...
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... Therefore, when an STA reads the Status Register, the STA is informed that the ICS1893CY-10 supports 10Base-T, half-duplex operations.) Bit 1.11 of the ICS1893CY-10 Status Register is a Command Override Write bit., which allows an STA to alter the default value of this bit. [See the description of bit 16.15, the Command Override Write Enable bit, in Section 7.11, “ ...
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... This default value ensures that bit 1.6 is backward compatible with the ICS1890, which does not have this capability. As the means of enabling this feature, the ICS1893CY-10 implements bit 1 Command Override Write bit, instead Read-Only bit as in the ICS1890. An STA uses the bit 1.6 to enable MF Preamble Suppression in the ICS1893CY-10 ...
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... Zero, then the ICS1893CY-10 sets bit 1.4 to logic zero. • One, then the ICS1893CY-10 sets bit 1.4 to logic one. In this case, the remote link partner is reporting the detection of a fault, which typically occurs when the remote link partner is having a problem with its receive channel ...
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... ICS1893CY-10 Data Sheet - Release 7.3.12 Jabber Detect (bit 1.1) The purpose of this bit is to allow an STA to determine if the ICS1893CY-10 detects a Jabber condition as defined in the ISO/IEC specification.The ICS1893CY-10 Jabber Detection function is controlled by the Jabber Inhibit bit in the 10Base-T Operations register (bit 18.5). To detect a Jabber condition, first the ICS1893CY-10 Jabber Detection function must be enabled. When bit 18.5 is logic: • ...
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... OUI bit 2.3 OUI bit 2.2 OUI bit 2.1 OUI bit 2.0 OUI bit ICS1893CY-10 Rev 1/07 Section 7.5, “Register 3: PHY Identifier Register” Section 7.5, “Register 3: PHY Identifier Register” Table 7-5, see Chapter 1, “Abbreviations and Access Function N/A N/A ...
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... ICS1893CY-10 Data Sheet - Release IEEE-Assigned Organizationally Unique Identifier (OUI) For each manufacturing organization, the IEEE assigns an 3-octet OUI. For Integrated Circuit Systems, Inc. the IEEE-assigned 3-octet OUI is 00A0BEh. The binary representation of an OUI is formed by expressing each octet as a sequence of eight bits, from least significant to most significant, and from left to right ...
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... The most-significant 6 bits of register 3 (that is, bits 3.15:10) include OUI bits 19 through 24. OUI bit 19 is stored in bit 3.15, while OUI bit 24 is stored in bit 3.10. 7.5.2 Manufacturer’s Model Number (bits 3.9:4) The model number for the ICS1893CY- (decimal stored in bit 3.9:4 as 00100b. ICS1893CY-10 Rev 1/07 Section 7.4, “Register 2: PHY Identifier ...
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... ICS1893CY-10 advertises (that is, exchanges) capability data with its remote link partner by using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged between PHYs when the ICS1893CY-10 has its Auto-Negotiation sublayer enabled. The value of the Link Control Word is established based on the value of the bits in this register. ...
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... Link Code Word that the ICS1893CY-10 exchanges with its remote link partner. The ICS1893CY-10 sets this bit to logic one whenever it detects a problem with the link, locally. The data in this register is sent to the remote link partner to inform it of the potential problem. If the ICS1893CY-10 does not detect a link fault, it clears bit 4.13 to logic zero. ...
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... ICS1893CY-10 advertises. The ICS1893CY-10 updates the Auto-Negotiation Advertisement Register TAF field to indicate the selection made by these pins. The ICS1893CY-10 sets only one of these four bits to logic one. The other three bits are a logic zero. Note: The ICS1893CY-10 does not alter the value of the Status Register bits ...
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... ICS1893CY-10 to provide these technologies. Note: 1. The ICS1893CY-10 does not alter the value of the Status Register bits based on the TAF bits in register 4, as the ISO/IEC definitions for the Status Register bits require these bits to indicate all the capabilities of the ICS1893CY-10 ...
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... During the auto-negotiation process, the ICS1893CY-10 advertises (that is, exchanges) the capability data with its remote link partner using a pre-defined Link Code Word. The value of the Link Control Word received from its remote link partner establishes the value of the bits in this register ...
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... Zero, it indicates that the remote link partner has not received the ICS1893CY-10 Link Control Word. • One, it indicates to the ICS1893CY-10 / STA that the remote link partner has acknowledged reception of the ICS1893CY-10 Link Control Word. 7.7.3 Remote Fault (bit 5.13) The ISO/IEC specification defines bit 5.13 as the Remote Fault bit. This bit is set based on the Link Control Word received from the remote link partner. When this bit is a logic: • ...
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... Writes to a reserved bit, the STA must use the default value specified in this data sheet. ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893CY-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that an STA always write the default value of any reserved bits during all management register write operations. ...
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... Next Page bit in its Link Control Word. 7.8.4 Next Page Able (bit 6.2) Bit 6 status bit that reports the capabilities of the ICS1893CY-10 to support the Next Page features of the auto-negotiation process. The ICS1893CY-10 sets this bit to a logic one to indicate that it can support these features ...
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... ICS1893CY-10 Data Sheet - Release 7.9 Register 7: Auto-Negotiation Next Page Transmit Register Table 7-14 lists the bits for the Auto-Negotiation Next Page Transmit Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893CY-10 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893CY-10 can comply with the message. 7.9.5 Toggle (bit 7.11) The Toggle (T) bit (bit 7.11) is used to synchronize the transmission of Next Page messages with the remote link partner ...
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... ICS1893CY-10 Data Sheet - Release 7.10 Register 8: Auto-Negotiation Next Page Link Partner Ability Register Table 7-15 lists the bits for the Auto-Negotiation Next Page Link Partner Ability Register, which establishes the contents of the Next Page Link Control Word that is transmitted during Next Page Operations. This table is compliant with the ISO/IEC specification ...
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... Zero, it indicates that the ICS1893CY-10 cannot comply with the message. • One, it indicates to the remote link partner that the ICS1893CY-10 can comply with the message. If the previous Next Page Link Control Word Toggle bit has a value of logic: • Zero, then the Toggle bit is set to logic one. ...
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... ICS1893CY-10 Data Sheet - Release 7.11 Register 16: Extended Control Register Table 7-16 lists the bits for the Extended Control Register, which the ICS1893CY-10 provides to allow an STA to customize the operations of the device. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Pins”). The PHY address is then latched into this register. (The value of each of the PHY Address bits is unaffected by a software reset.) 7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5) The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893CY-10 to lose LOCK, thereby requiring the Stream Cipher Scrambler to resynchronize. 7.11.5 ICS Reserved (bit 16.4) See Section 7.11.2, “ ...
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... ICS1893CY-10 Data Sheet - Release 7.11.7 Invalid Error Code Test (bit 16.2) The Invalid Error Code Test bit allows an STA to force the ICS1893CY-10 to transmit symbols that are typically classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC 4B/5B definition ...
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... Note: 1. For an explanation of acronyms used in 2. Most of this register’s bits are latching high or latching low, which allows the ICS1893CY-10 to capture and save the occurrence of an event for an STA to read. (For more information on latching high and latching low bits, see Section 7.1.4.1, “ ...
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... ICS1893CY-10 Data Sheet - Release 7.12.1 Data Rate (bit 17.15) The Data Rate bit indicates the ‘selected technology’. If the ICS1893CY-10 is in: • Hardware mode, the value of this bit is determined by the 10/100SEL input pin. • Software mode, the value of this bit is determined by the Data Rate bit 0.13. ...
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... This bit has no definition in 10Base-T mode. 7.12.5 100Base PLL Lock Error (bit 17.9) The Phase-Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1893CY-10 has ever experienced a PLL Lock Error. A PLL Lock Error occurs when the PLL fails to lock onto the incoming 100Base data stream. If this bit is set to a logic: • ...
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... When the ICS1893CY-10 is receiving a packet, it examines each received Symbol to ensure the data is error free error occurs, the port indicates this condition to the MAC/repeater by asserting the RXER signal. In addition, the ICS1893CY-10 sets its Invalid Symbol bit to logic one. Therefore, if this bit is set to a logic: • ...
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... The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream by the ICS1893CY-10. During reception of a valid packet, the ICS1893CY-10 examines each symbol to ensure that the data being passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates this condition to the MAC/repeater by setting this bit ...
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... Squelch inhibit 7.13.1 Remote Jabber Detect (bit 18.15) The Remote Jabber Detect bit is provided to indicate that an ICS1893CY-10 port has detected a Jabber Condition on its receive path. This bit is reset to logic zero on a read of the 10Base-T operations register. When this bit is logic: • ...
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... ICS1893CY-10 - Release 7.13.2 Polarity Reversed (bit 18.14) The Polarity Reversed bit is used to inform an STA whether the ICS1893CY-10 has detected that the signals on the Twisted-Pair Receive Pins (TP_RXP and TP_RXN) are reversed. When the signal polarity is: • Correct, the ICS1893CY-10 sets bit 18. logic zero. ...
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... This bit is a control bit and not a status bit. Therefore not updated to indicate this automatic inhibiting of the SQE test in full-duplex mode or repeater mode. 7.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1893CY-10 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • ...
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... ICS1893CY-10 - Release 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893CY-10 operations. Note: 1. For an explanation of acronyms used in 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits ...
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... Section 7.11.2, “ICS Reserved (bits 7.14.5 Auto-MDI/MDIX (bits 19. 9:8) (New) The ICS1893CY-10 includes the Auto-MDI/MDIX crossover feature. The Auto-MDI/MDIX feature automatically selects the correct MDI or MDIX configuration to match the cable plant by automatically swapping transmit and receive signal pairs at the PHY. Auto-MDI/MDIX is defaulted on but may be disabled for test purposes using either the AMDIX_EN (pin 10 writing (bits 19 ...
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... MDIO register 13h bit 9 MDI_MODE [19:8] MDIO register 13h bit 8 7.14.6 Twisted Pair Tri-State Enable, TPTRI (bit 19.7) The ICS1893CY-10 provides a Twisted Pair Tri-State Enable bit. This bit forces the TP_TXP and TP_TXN signals to a high-impedance state. When this bit is set to logic: • ...
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... ICS1893CY-10 Data Sheet - Release Chapter 8 Pin Diagram, Listings, and Descriptions 8.1 ICS1893CY-10 Pin Diagram NOD/REP 1 10/100SEL 2 AMDIX_EN 3 VSS 4 TP_AP 5 TP_AN 6 VDD 7 VDD 8 TP_BN 9 TP_BP 10 VSS 11 VDD 12 10TCSR 13 100TCSR 14 VSS 15 VDD 16 ICS1893CY-10 Rev 1/07 Chapter 8 Pin Diagram, Listings, and Descriptions ICS1893CY-10 Copyright © 2007, Integrated Device Technology, Inc. ...
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... ICS1893CY-10 - Release 8.2 ICS1893CY-10 Pin Listings Table 8-1 lists the ICS1893CY-10 pins by pin number. Table 8-1. ICS1893CY-10 Pins, by Pin Number Pin Pin Name No. 1 NOD/REP 2 10/100SEL 3 AMDIX_EN 4 VSS 5 TP_AP 6 TP_AN 7 VDD 8 VDD 9 TP_BN 10 TP_BP 11 VSS 12 VDD 13 10TCSR 14 100TCSR 15 VSS 16 VDD ICS1893CY-10 Rev 1/07 ...
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... Transformer Interface Pins Transformer connections on the ICS1893CY-10 signals TP_AP, TP_AN, TP_BP and TP_BN are shown in Table 8.2. The previous TP_CT pin on the ICS1893AF is not used with the ICS1893CY-10. The typical Twisted Pair Transformers connections are shown in Chapter 5. The transformer must be 1:1 ratio and symetrical for 10/100 MDI/MDIX applications since the transmit twisted pair and receive twisted pair are interchangeable ...
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... Note: 1. During either a power-on reset or a hardware reset, each multi-function configuration pin is an input that is sampled when the ICS1893CY-10 exits the reset state. After sampling is complete, these pins are output pins that can drive status LEDs software reset does not affect the state of a multi-function configuration pin. During a software reset, all multi-function configuration pins are outputs ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893CY-10 when either hardware mode or software mode. – An output pin following reset. In this case, this pin provides collision status for the ICS1893CY-10. ...
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... This multi-function configuration pin is: – An input pin during either a power-on reset or a hardware reset. In this case, this pin configures the ICS1893CY-10 when either hardware mode or software mode. – An output pin following reset. In this case, the pin provides activity status of the ICS1893CY-10. ...
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... ICS1893CY-10 Data Sheet - Release 8.3.3 Configuration Pins Table 8-4 lists the configuration pins. Table 8-4. Configuration Pins Pin Pin Name Number Type 10/100SEL 2 Input or Output AMDIX_E 3 Input N 10TCSR 13 Input 100TCSR 14 Input ANSEL 26 Input or Output ICS1893CY-10 Rev 1/07 Chapter 8 Pin Diagram, Listings, and Descriptions ...
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... High, this pin selects Software mode operations. (Stream Cipher) Lock (Acquired). When the signal on this pin is logic: • Low, the ICS1893CY-10 does not have a lock on the data stream. • High, the ICS1893CY-10 has a lock on the data stream. Link Status. This pin is used to report the status of the link segment. When the signal on this pin is logic: • ...
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... Reference Output. This pin is used with a crystal. (System) Reset (Active Low). • When the signal on this active-low pin is logic: – Low, the ICS1893CY- hardware reset. – High, the ICS1893CY-10 is operational. • For more information on hardware resets, see the following: – ...
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... The ICS1893CY-10, to transfer status information. All transfers and sampling are synchronous with the signal on the MDC pin. Note: If the ICS1893CY- used in an application that uses the mechanical MII specification, MDIO must have a 1.5 k Ω ±5% pull-up resistor at the ICS1893CY-10 end and Ω ±5% pull-down resistor at the station management end ...
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... The ICS1893CY-10 sources the RXCLK to the MAC/repeater interface. The ICS1893CY-10 uses RXCLK to synchronize the signals on the following pins: RXD[3:0], RXDV, and RXER. The following table contrasts the behavior on the RXCLK pin when the mode for the ICS1893CY-10 is either 10Base-T or 100Base-TX. 10Base-T The RXCLK frequency is 2 ...
Page 109
... Low, the MAC indicates that it is not in a tri-state condition. • High, the MAC indicates that tri-state condition. In this case, the ICS1893CY-10 acts to ensure that only one PHY is active at a time. Transmit Clock. The ICS1893CY-10 generates this clock signal to synchronize the transfer of data from the MAC/Repeater Interface to the ICS1893CY-10 ...
Page 110
... MII mode, TXER is not used. • 100M MII mode: – The ICS1893CY-10 synchronously samples its TXER signal on the rising edges of its TXCLK signal. – The assertion of TXER by the MAC/repeater causes the ICS1893CY-10 to transmit an Invalid Symbol. – the Invalid Error Code Test bit (bit 16.2) is set to logic one, the 5-bit ...
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... Low, the MAC indicates it is not in a tri-state condition. • High, the MAC indicates tri-state condition. In this case, the ICS1893CY-10 acts to ensure that only one PHY is active at a time. (A PHY address of 00 also tri-states the MII interface.) Output Symbol Transmit Clock. ...
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... Management Data Input/Output. Output This pin’s description is the same as that given in Output 10M Receive Clock. In 10M Serial mode, the ICS1893CY-10 sources the 10RCLK to its MAC/repeater Interface. The 10RCLK synchronizes the data on the 10RD0 pin between the ICS1893CY-10 and the MAC/repeater. • ...
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... High, the MAC indicates that tri-state condition. In this case, the ICS1893CY-10 acts to ensure that only one PHY is active at a time. • If the PHY address is 00, the ICS1893CY-10 acts as if the RX-TRI pin is held high. Output 10M (Serial Interface) Transmit Clock. ...
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... ICS1893CY-10 Data Sheet - Release 8.3.5 Reserved Pins Table 8-8 lists the reserved pins. Table 8-8. Reserved Pins Pin Pin Pin Name Number Type REG 20 Input 8.3.6 Ground and Power Pins Table 8-9 lists the ground and power pins. Table 8-9. Ground and Power Pins ...
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... Stresses above these ratings can permanently damage the ICS1893CY-10. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the ICS1893CY-10 at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability ...
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... ICS1893CY-10 Data Sheet - Release 9.3 Recommended Component Values * Table 9-3. Recommended Component Values for ICS1893CY-10 Parameter Oscillator Frequency 10TCSR Resistor Value 100TCSR Resistor Value LED Resistor Value † There are two IEEE Std 802.3 requirements that drive the tolerance for the frequency of the oscillator. ...
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... Power-Down Supply Current† Reset † These supply current parameters are measured through VDD pins to the ICS1893CY-10. The supply current parameters include external transformer currents. ‡ Measurements taken with 100% data transmission and the minimum inter-packet gap. 9.4.2 DC Operating Characteristics for TTL Inputs and Outputs Table 9-5 lists the 3 ...
Page 118
... Table 9-8. REF_IN Timing Time Parameter Period t1 REF_IN Duty Cycle t2 REF_IN Period Figure 9-2. REF_IN Timing Diagram REF_IN ICS1893CY-10 Rev 1/07 Chapter 9 DC and AC Operating Conditions Conditions – – Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 119 Figure 9-2 Min ...
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... ICS1893CY-10 Data Sheet - Release 9.5.2 Timing for Transmit Clock (TXCLK) Pins Table 9-9 lists the significant time periods for signals on the Transmit Clock (TXCLK) pins for the various interfaces. Figure 9-3 shows the timing diagram for the time periods. Table 9-9. Transmit Clock Timing ...
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... RXCLK Period t2c RXCLK Period t2d RXCLK Period Figure 9-4. Receive Clock Timing Diagram t1 RXCLK ICS1893CY-10 Rev 1/07 Chapter 9 DC and AC Operating Conditions Conditions – 100M MII (100Base-TX) 10M MII (10Base-T) 100M Symbol Interface (100Base-TX) 10M Serial Interface (10Base-T) t2 Copyright © 2007, Integrated Device Technology, Inc. ...
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... ICS1893CY-10 Data Sheet - Release 9.5.4 100M MII / 100M Stream Interface: Synchronous Transmit Timing Table 9-11 lists the significant time periods for the 100M MII / 100M Stream Interface synchronous transmit timing. The time periods consist of timings of signals on the following pins: • TXCLK • ...
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... TXD[3:0], TXEN, TXER Setup to TXCLK Rise t2 TXD[3:0], TXEN, TXER Hold after TXCLK Rise Figure 9-6. 10M MII Synchronous Transmit Timing Diagram TXCLK TXD[3:0] TXEN TXER ICS1893CY-10 Rev 1/07 Parameter Conditions t1 t2 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 123 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893CY-10 Data Sheet - Release 9.5.6 MII / 100M Stream Interface: Synchronous Receive Timing Table 9-13 lists the significant time periods for the MII / 100M Stream Interface synchronous receive timing. The time periods consist of timings of signals on the following pins: • RXCLK • RXD[3:0] • ...
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... MDC Rise Time to MDIO Valid t5 MDIO Setup Time to MDC t6 MDIO Hold Time after MDC † The ICS1893CY-10 is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading of MDC. Figure 9-8. MII Management Interface Timing Diagram MDC t1 ...
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... ICS1893CY-10 Data Sheet - Release 9.5.8 10M Serial Interface: Receive Latency Table 9-15 lists the significant time periods for the 10M Serial Interface timing. The time periods consist of timings of signals on the following pins: • TP_RX (the MDI mapping of the 10M/100M MII TP_RXP and TP_RXN pins) • ...
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... Figure 9-10. 10M MII Receive Latency Timing Diagram † TP_RX RXCLK RXD 5 † Manchester encoding is not shown. ICS1893CY-10 Rev 1/07 Parameter Conditions 10M MII 5 t1 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 127 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893CY-10 Data Sheet - Release 9.5.10 10M Serial Interface: Transmit Latency Table 9-17 lists the significant time periods for the 10M Serial Interface transmit latency. The time periods consist of timings of signals on the following pins: • 10TXEN (the 10M Serial Interface mapping of the 10M/100M MII TXEN pins) • ...
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... Figure 9-12. 10M MII Transmit Latency Timing Diagram TXEN TXCLK TXD † TP_TX † Manchester encoding is not shown. ICS1893CY-10 Rev 1/07 Parameter Conditions 10M MII Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 129 Chapter 9 DC and AC Operating Conditions Min ...
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... ICS1893CY-10 Data Sheet - Release 9.5.12 MII / 100M Stream Interface: Transmit Latency Table 9-19 lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • TXD (that is, TXD[3:0]) • ...
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... TXEN Sampled Asserted to CRS Assert t2 TXEN De-Asserted to CRS De-Asserted Figure 9-14. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) TXEN TXCLK CRS t1 ICS1893CY-10 Rev 1/07 Chapter 9 DC and AC Operating Conditions Parameter t2 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 131 Condi- Min. ...
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... ICS1893CY-10 Data Sheet - Release 9.5.14 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 9-21 lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • ...
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... Figure 9-16. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram † TP_RX RXCLK RXD † Shown unscrambled. ICS1893CY-10 Rev 1/07 Chapter 9 DC and AC Operating Conditions Conditions t1 t2 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 133 Min. Typ. Max. ...
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... ICS1893CY-10 Data Sheet - Release 9.5.16 100M Media Dependent Interface: Input-to-Carrier Assertion/De-Assertion Table 9-23 lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The time periods consist of timings of signals on the following pins: • TP_RX (that is, TP_RXP and TP_RXN) • CRS • ...
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... Table 9-24. Power-On Reset Timing Time Period VDD ≥ 2 Reset Complete t1 Figure 9-18. Power-On Reset Timing Diagram 2.7 V VDD TXCLK Valid ICS1893CY-10 Rev 1/07 Parameter Conditions t1 Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 135 Chapter 9 DC and AC Operating Conditions Min. Typ. ...
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... ICS1893CY-10 Data Sheet - Release 9.5.18 Reset: Hardware Reset and Power-Down Table 9-25 lists the significant time periods for the hardware reset and power-down reset. The time periods consist of timings of signals on the following pins: • REF_IN • RESETn • TXCLK Figure 9-19 shows the timing diagram for the time periods ...
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... COL Heartbeat Assertion Delay from TXEN De-Assertion t2 COL Heartbeat Assertion Duration Figure 9-20. 10Base-T Heartbeat (SQE) Timing Diagram TXEN TXCLK COL ICS1893CY-10 Rev 1/07 Chapter 9 DC and AC Operating Conditions Section 6.5.10, “10Base-T Operation: SQE Conditions 10Base-T Half Duplex 10Base-T Half Duplex t1 t2 Copyright © ...
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... ICS1893CY-10 Data Sheet - Release 9.5.20 10Base-T: Jabber Timing Table 9-27 lists the significant time periods for the 10Base-T jabber. The time periods consist of timings of signals on the following pins: • TXEN • TP_TX (that is, TP_TXP and TP_TXN) • COL Figure 9-21 shows the timing diagram for the time periods. ...
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... Table 9-28. 10Base-T Normal Link Pulse Timing Time Period t1 Normal Link Pulse Width t2 Normal Link Pulse to Normal Link Pulse Period Figure 9-22. 10Base-T Normal Link Pulse Timing Diagram TP_TXP ICS1893CY-10 Rev 1/07 Figure 9-22 shows the timing diagram for the time periods. Parameter Conditions 10Base-T 10Base Copyright © ...
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... ICS1893CY-10 Data Sheet - Release 9.5.22 Auto-Negotiation Fast Link Pulse Timing Table 9-29 lists the significant time periods for the ICS1893CY-10 Auto-Negotiation Fast Link Pulse. The time periods consist of timings of signals on the following pins: • TP_TXP • TP_TXN Figure 9-23 shows the timing diagram for one pair of these differential signals, for example TP_TXP minus TP_TXN ...
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... ICS1893CY-10 - Release Chapter 10 ICS1893CY-10 Package Physical Dimensions Figure 10-1. ICS1893CY-10 Physical Dimensions ICS1893CY-10 Rev 1/07 Chapter 10 ICS1893CY-10 Package Physical Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 141 ...
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... ICS1893CY-10 Data Sheet - Release Chapter 11 Ordering Information Figure 11-1. ICS1893CY-10 Ordering Information Part / Order Number ICS1893CY-10 ICS1893CYI-10 ICS1893CY-10LF ICS1893CYI-10LF ICS1893CY-10 Rev 1/07 Marking Package 1893CY-10 10x10 TQFP (Thin Quad Flat Pack) 1893CYI-10 10x10 TQFP (Thin Quad Flat Pack) 1893CY-10LF 10x10 TQFP Lead Free ...
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... ICS1893CY-10 - Release Integrated Device Technology, Inc. Corporate Headquarters: ICS1893CY-10 Rev 1/07 6024 Silver Creek Valley Rd. San Jose, CA 95138 www.idt.com Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 143 Chapter 11 Ordering Information ...
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... ICS1893CY-10 Data Sheet - Release ICS1893CY-10 Rev A 11/06 Copyright © 2006, Integrated Device Technology, Inc. All rights reserved. 144 Chapter 11 Ordering Information ...