ICS1893CY-10LFT IDT, Integrated Device Technology Inc, ICS1893CY-10LFT Datasheet - Page 62

• Manufacturer Part Number: ICS1893CY-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893CY-10LFT

7.2.5 Low Power Mode (bit 0.11)
7.2.6 Isolate (bit 0.10)
7.2.7 Restart Auto-Negotiation (bit 0.9)
ICS1893CY-10 Rev 1/07
This bit provides one way to control the ICS1893CY-10 low-power mode function. When bit 0.11 is logic:
•
•
Note:
This bit controls the ICS1893CY-10 Isolate function. When bit 0.10 is logic:
•
•
The default value for bit 0.10 depends upon the PHY address of
•
•
This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is
logic one). When bit 0.12 is logic:
•
•
Zero, there is no impact to ICS1893CY-10 operations.
One, the ICS1893CY-10 enters the low-power mode. In this case, the ICS1893CY-10 disables all internal
functions and drives all MAC/repeater output pins low except for those that support the MII Serial
Management Port. In addition, the ICS1893CY-10 internally activates the TPTRI function to tri-state the
signals on the Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.
Zero, there is no impact to ICS1893CY-10 operations.
One, the ICS1893CY-10 electrically isolates its data paths from the MAC/Repeater Interface. The
ICS1893CY-10 places all MAC/repeater output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL,
and CRS) in a high-impedance state and it isolates all MAC/repeater input signals (TXD[3:0], TXEN, and
TXER). In this mode, the Serial Management Interface continues to operate normally (that is, bit 0.10
does not affect the Management Interface).
Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893CY-10 isolates itself
from the MAC/Repeater Interface.
Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893CY-10 does not
isolate its MAC/Repeater Interface.
Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893CY-10 isolates any attempt by the STA
to set bit 0.9 to logic one.
One (as set by an STA), the ICS1893CY-10 restarts the auto-negotiation process. Once the
auto-negotiation process begins, the ICS1893CY-10 automatically sets this bit to logic zero, thereby
providing the self-clearing feature.
ICS1893CY-10 Data Sheet - Release
There are two ways the ICS1893CY-10 can enter low-power mode. When entering low-power
mode:
•
•
By setting bit 0.11 to logic one, the ICS1893CY-10 maintains the value of all Management
Register bits except the latching high (LH) and latching low (LL) status bits, which are
re-initialized to their default values instead. (For more information on latching high and latching
low bits, see
During a reset, the ICS1893CY-10 sets all management register bits to their default values.
Section 7.1.4.1, “Latching High Bits”
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
62
and
Section 7.1.4.2, “Latching Low
Table
7-16. If the PHY address:
Chapter 7 Management Register Set
Bits”.)