ICS1893CY-10LFT IDT, Integrated Device Technology Inc, ICS1893CY-10LFT Datasheet - Page 94

• Manufacturer Part Number: ICS1893CY-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893CY-10LFT

7.13.7 SQE Test Inhibit (bit 18.2)
7.13.8 Link Loss Inhibit (bit 18.1)
7.13.9 Squelch Inhibit (bit 18.0)
ICS1893CY-10 Rev 1/07
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
•
•
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
The Link Loss Inhibit bit allows an STA to prevent the ICS1893CY-10 from dropping the link in 10Base-T
mode. When an STA sets this bit to logic:
•
•
The Squelch Inhibit bit allows an STA to control the ICS1893CY-10 Squelch Detection in 10Base-T mode.
When an STA sets this bit to logic:
•
•
Zero, the ICS1893CY-10 enables its SQE Test generation.
One, the ICS1893CY-10 disables its SQE Test generation.
Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
One, the ICS1893CY-10 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
One, before the ICS1893CY-10 can establish a valid link, the ICS1893CY-10 must receive valid
10Base-T data.
Zero, before the ICS1893CY-10 can establish a valid link, the ICS1893CY-10 must receive both valid
10Base-T data followed by an IDL.
functionality of this bit.
inhibiting of the SQE test in full-duplex mode or repeater mode.
ICS1893CY-10 Data Sheet - Release
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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Chapter 7 Management Register Set