ICS1893CY-10LFT IDT, Integrated Device Technology Inc, ICS1893CY-10LFT Datasheet - Page 108

• Manufacturer Part Number: ICS1893CY-10LFT
• Description: PHYCEIVER LOW PWR 3.3V 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893CY-10LFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: 1893CY-10LFT

ICS1893CY-10 Rev 1/07
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
RXCLK
RXD0
RXD1
RXD2
RXD3
RXDV
Name
Pin
ICS1893CY-10 Data Sheet - Release
Number
Pin
38
35
34
33
32
36
Output
Output
Output
Type
Pin
Copyright © 2007, Integrated Device Technology, Inc.
Receive Clock.
The ICS1893CY-10 sources the RXCLK to the MAC/repeater interface.
The ICS1893CY-10 uses RXCLK to synchronize the signals on the
following pins: RXD[3:0], RXDV, and RXER. The following table contrasts
the behavior on the RXCLK pin when the mode for the ICS1893CY-10 is
either 10Base-T or 100Base-TX.
Receive Data 0–3.
Receive Data Valid.
The ICS1893CY-10 asserts RXDV to indicate to the MAC/repeater that
data is available on the MII Receive Bus (RXD[3:0]). The ICS1893CY-10:
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
•
•
•
•
RXD0 is the least-significant bit and RXD3 is the most-significant bit of
the MII receive data nibble.
While the ICS1893CY-10 asserts RXDV, the ICS1893CY-10 transfers
the receive data signals on the RXD0–RXD3 pins to the
MAC/Repeater Interface synchronously on the rising edges of RXCLK.
Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see
100M Stream Interface: Synchronous Receive
De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
The RXCLK frequency is 2.5
MHz.
The ICS1893CY-10 generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893CY-10 switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893CY-10 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
The RXCLK aligns once per
packet.
All rights reserved.
10Base-T
108
Chapter 8 Pin Diagram, Listings, and Descriptions
Pin Description
The RXCLK frequency is 25 MHz.
The ICS1893CY-10 generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the
ICS1893CY-10 uses the REF_IN
clock to generate the RXCLK.
While the ICS1893CY-10 is
bringing up a link, a clock phase
change of up to 360 degrees can
occur.
The RXCLK aligns once, when
the link is being established.
100Base-TX
Chapter 9.5.6, “MII /
Timing”.)