ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 23

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

eICE Debug Interface
11 February 2010
The eICE debug interface provides a serial communication interface allowing an external device (the
eICE master) to have read and write access in the memory and register space of the eCOG1 (slave),
and to control the CPU state and program execution with various debug commands. Access to
memory and registers can take place in real time, with the CPU running or halted.
eICE functions include:
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The eICE debug interface requires only a 10-pin header on the target system. A low cost USB eICE
adaptor plugs into this header and connects to the host PC via USB. This adaptor is used by the
CyanIDE software development tool, allowing single stepping at C source code level and inspection or
modification of variables or memory, while running the application on the target system.
Address
0x56
0x58
0x5A
0x5C
0x5E
0x60
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
0x78
0x7A
0x7C
0x7E
Interactive, real time debug.
Non-intrusive (real time) access to memory and CPU registers.
Single or double word memory accesses anywhere in CPU logical code and data spaces.
Run/Step/Stop commands to control program execution.
Address error detection.
32 bit data ICE operations.
Synchronised (deterministic) access mode available by inserting instructions in code.
Hardware address and data breakpoint registers.
Flash programming.
Version register to identify ICE interface.
Interrupt
_int_usarta_tx_rdy
_int_usartb_rx_rdy
_int_usartb_tx_rdy
_int_sci_tx_done
_int_sci_tx_err
_int_sci
_int_ifr_tx_done
_int_ifr_rx_done
_int_ifr_rx_err
_int_ifr_frame_done
_int_uart1a_tx_rdy
_int_uart1a_rx_rdy
_int_uart1b_tx_rdy
_int_uart1b_rx_rdy
_int_uart2a_tx_rdy
_int_uart2a_rx_rdy
_int_uart2b_tx_rdy
_int_uart2b_rx_rdy
_int_ehi
_int_gpio
_int_dsci
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
Source
DUSART channel A transmit port ready
DUSART channel B receive port ready
DUSART channel B transmit port ready
DUSART smart card transmit data complete
DUSART smart card transmit error detected
DUSART general smart card interrupt
DUSART infrared transmit data complete
DUSART infrared receive data complete
DUSART infrared receive error detected
DUSART infrared frame complete
UART1A transmit port ready
UART1A receive port ready
UART1B transmit port ready
UART1B receive port ready
UART2A transmit port ready
UART2A receive port ready
UART2B transmit port ready
UART2B receive port ready
EHI module interrupt.
GPIO interrupt (edge or level detect)
DSCI interrupt (dual smart card interface)
www.cyantechnology.com
Table 17: Interrupt vectors
Version 1.17
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