ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 33

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

Dual Smart Card Interface
Ethernet MAC
11 February 2010
The Dual Smart Card Interface (DSCI) module provides two complete smart card interface peripherals,
independent of the single SCI function available within the DUSART peripheral.
The DSCI peripheral has the following main features.
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The eCOG1X includes an Ethernet MAC peripheral which can be used with a suitable external PHY
device.
The main features of the EMAC peripheral include:
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The EMAC peripheral contains four main functional blocks.
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Both the transmit and receive data paths have their own separate 128 byte FIFO to provide data flow
buffering. Data packets are stored in internal SRAM, accessed via the DMA controller. The DMA
controller is managed through registers in the eCOG1X internal peripheral register space.
The EMAC peripheral is controlled through a set of control/status registers (CSRs), located at an
address defined by the MMU. Access to these registers is possible only when the MMU has been
configured to set the base address for these registers in data space, and the SSM has been configured
to provide a suitable clock signal to the EMAC.
Two independent smart card interface blocks. The only shared resources are the common
peripheral clock and reset (from the SSM), and the interrupt vector.
Flexible smart card clock generation with support for clock stop. The smart card clock is derived
from the DSCI peripheral clock. Its frequency can be changed while running, either by changing
the DSCI peripheral clock in the SSM, or by changing the smart card clock prescaler in the DSCI.
Dedicated serial port for each smart card.
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Card activation and deactivation sequences, with manual or automatic start on card insertion and
removal.
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Flexible software interface with interrupt support.
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Supports both 10Mbits/s and 100Mbits/s operation with the appropriate external PHY device
fitted.
Media Independent Interface (MII) for PHY device configuration.
Complies with IEEE 802.3 CSMA/CD standard.
Single address filtering.
Buffer descriptors may be arranged as a ring or a chain.
Control/status registers.
DMA controller.
Transmit data path.
Receive data path.
Programmable bit polarity and character endianness.
Programmable guard time insertion from 1 to 256 etus.
Programmable baud rate derived from the DSCI peripheral clock.
Parity generation and checking (even or odd parity).
Double buffered receive and transmit data registers.
Programmable receive character timeout. This feature can be used for the EMV Work
Waiting Time function in the T=0 protocol, or for the Character Waiting Time and/or Block
Waiting Time functions in the T=1 protocol.
Programmable error detection and retransmission support for the T=0 protocol.
Programmable delay times for activation and deactivation sequences.
Programmable polarity for card detect, reset and power enable signals.
The DSCI can be deactivated to reduce power consumption until a card is inserted.
Card insertion and removal.
Card activation and deactivation sequence complete.
Received data available.
Transmitter ready.
Error conditions
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
www.cyantechnology.com
Version 1.17
33