ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 66

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

Version 1.17
66
EHI_D0..D16/D32
Symbol
EHI_A0..A2/A7
EHI_D0..D16/D32
t
t
t
t
t
t
t
t
t
WW
CW
WC
t
DH
AS
AH
DV
DZ
DS
CI
External Host Interface (EHI)
MMP mode
The table below for the eICE debug port uses the symbol T
EHI_A0..A2/A7
EHI_WAIT
EHI_RW
EHI_CS
EHI_WAIT
EHI_RW
EHI_CS
Parameter
Setup time host address valid to EHI_CS active
Hold time EHI_CS inactive to host address invalid
Delay time EHI_CS active to EHI_WAIT active
Minimum EHI_WAIT active width
Delay time EHI_WAIT inactive to EHI_CS inactive
Minimum time data output valid before EHI_WAIT inactive
Delay time EHI_CS inactive to data output invalid
Setup time data input valid to EHI_CS inactive
Hold time EHI_CS inactive to data input invalid
Minimum EHI_CS inactive time
t
AS
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
t
AS
t
CW
address(n)
t
CW
address(n)
Figure 15: EHI MMP write cycle timing diagram
Figure 14: EHI MMP read cycle timing diagram
Table 32: AC characteristics - EHI MMP mode
t
eCOG1X Microcontroller Product Family
WW
t
WC
t
t
DV
WW
data(n)
t
WC
t
DS
data(n)
t
AH
t
DZ
www.cyantechnology.com
t
AH
t
DH
t
CI
t
CI
t
AS
t
AS
t
CW
t
CW
address(n+1)
address(n+1)
CPU
t
WW
t
WW
for the CPU clock period.
data(n+1)
t
DV
data(n+1)
t
WC
t
DS
T
3 x T
3 x T
t
WC
CPU
Min
13
0
0
0
5
3
t
t
CPU
CPU
AH
AH
– 5
t
t
DZ
DH
11 February 2010
Max
12
From Ext. Host
From Ext. Host
From Ext. Host
From Ext. Host
From eCOG1
From Ext. Host
From Ext. Host
From Ext. Host
From eCOG1
From eCOG1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns