ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 27

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

DUARTs
11 February 2010
PWM
The two PWM timers are implemented as 16-bit down counters. An interrupt is generated when the
timer passes a ‘transition’ value stored in one of the configuration registers, and a second interrupt is
generated when the timer passes zero. The count duration may be preset or reset at any time.
When enabled, the PWM timers count at their input clock frequencies, set by the SSM. The PWM
output signal inverts on each interrupt (transition or zero value). The sense of the output signal is
programmable.
Typical applications are to generate a variable frequency output or a pulse width modulated output.
Note that by adding an external low-pass filter, it is possible to use a PWM output as a low speed
digital-to-analogue converter (DAC).
Capture Timer
The input capture timer CAP is a 16-bit up counter. An interrupt is generated when the timer wraps
around to zero, and it may be reset to zero at any time. When enabled, the capture timer counts at its
input clock rate, set by the SSM.
The capture timer value is transferred to one of the six capture registers when an edge is detected on
one of the six capture inputs. Capture inputs 1-4 store all 16 bits of the capture timer value, while
capture inputs 5 and 6 store only the high 8 bits of the capture timer value.
Watchdog Timer
The watchdog timer WDOG is a 16-bit down counter. The count duration may be preset to a new value
or reset to the current period value at any time. When enabled, the watchdog timer counts at its input
clock frequency, set by the SSM.
When the watchdog timer reaches zero for the first time, a watchdog timeout exception interrupt is
generated and the counter restarts automatically to begin a new countdown period. If the watchdog
timer reaches zero for a second time without being restarted by the application software, then a
hardware watchdog timeout reset signal is generated on the power-on reset output pin (nRESET or
nRESET_OUT).
Long Interval Timer
The long interval timer LTMR is a 24-bit down counter, allowing a maximum count of 2
is generated when the timer passes zero. The upper 16 bits of the timer may be set at any time to the
value in a load register; the lower 8 bits are reset to zero when the upper 16 bits are written. When
enabled, the long interval timer counts at its input clock frequency, set by the SSM.
The eCOG1X includes two identical DUART modules, DUART1 and DUART2. Each DUART module
provides two separate UART channels, labelled A and B.
The four UART channels support the following features:
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Programmable format: 5, 6, 7 or 8 data bits; 1, 1.5 or 2 stop bits; even, odd or no parity.
Programmable baud rate divider.
8-bit and 16-bit transmit data registers (one and two data frames).
Interrupts generated on transmit ready and overflow.
8-bit receive data register (one data frame) with two byte receive FIFO.
Receive data ready interrupt generated on one or two bytes received.
Oversampled received data with noise filter.
Receiver error detection for false start bits, parity and frame errors.
Configurable data signal polarities.
Receive timeout detection of 1 to 63 bit periods.
Line Break (15 consecutive data zero bits) generation in software, detection in hardware.
Prescaled UART clock to reduce power consumption.
Power saving features to start the UART clock automatically when the receiver detects a start bit
and to hold the clock active during transmission.
Operates independently of the CPU, allowing the CPU to be put to sleep while the DUART
transmit or receive is still active.
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
www.cyantechnology.com
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. An interrupt
Version 1.17
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