PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 126

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.7.4
The Command/Indication channel carries real-time status information between the
IPAC-X and another device connected to the IOM-2 interface.
1. One C/I channel (called C/I0) conveys the commands and indications between the
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
being generated anytime a change occurs (ISTA.CIC). A new code must be found in two
consecutive IOM-2 frames to be considered valid and to trigger a C/I code change
interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
2. A second C/I channel (called C/I1) can be used to convey real time status information
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
CIC Interrupt Logic
Figure 71
A CIC interrupt may originate:
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC 1).
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
Data Sheet
layer-1 and the layer-2 parts of the IPAC-X. It can be accessed by an external layer-
2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration
is done in IOM-2 channel 2 (see
between the IPAC-X and various non-layer-1 peripheral devices, e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction. The width
can be changed from 4bit to 6bit by setting bit CIX1.CICW.
shows the CIC interrupt structure.
C/I Channel Handling
Figure
126
49).
Description of Functional Blocks
PSB/PSF 21150
Chapter
2003-01-30
IPAC-X
3.5.4.