PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 15

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Monitor channel
programming
C/I channels
Layer 1 state machine
Layer 1 state machine
in software
Support of IDSL (144kBit/s) Provided
D-channel HDLC support
D-channel FIFO size
B-channel HDLC support
B-channel FIFO size
Reset Sources
Interrupt Output Signals
Data Sheet
IPAC-X PSB 21150
Provided
(MON0, 1, 2, ..., 7)
CI0 (4 bit),
CI1 (4/6 bit)
With changes for
correspondence with the
actual ITU specification
Possible
(HDLC controller access,
SDS1/2 signals active)
D- and B-channel timeslots;
non-auto mode,
transparent mode 0-2,
extended transparent mode
64 bytes cyclic buffer per
direction with
programmable FIFO
thresholds
D- and B-channel timeslots;
non-auto mode,
transparent mode 0-2,
extended transparent mode
128 bytes cyclic buffer per
direction for each channel
with programmable FIFO
thresholds
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
INT
low active (open drain) by
default, reprogrammable to
high active (push-pull)
15
IPAC PSB 2115
Provided
(MON0 or 1)
CI0 (4 bit),
CI1 (6 bit)
Not possible
Not provided
D-channel timeslot;
auto mode,
non-auto mode,
transparent mode 1-3
2x32 bytes buffer per
direction
D-channel timeslot;
non-auto mode,
transparent mode 0,1
extended transparent mode
2x64 bytes buffer per
direction
RST Input
Watchdog
C/I Code Change
EAW Pin
Low active INT
PSB/PSF 21150
2003-01-30
Overview
IPAC-X