PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 191

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TR_
STA
Outside the active window of SGO (defined in SGD) the level on pin SGO remains in the
“stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if SGP=0) or SGO=0
(if SGP=1) outside the active window.
4.2.4
Value after reset: 00
Important: This register is used only if the Layer 1 state machine of the IPAC-X is
disabled (TR_CONF0.L1SW = 1) and implemented in software! With the IPAC layer 1
state machine enabled, the signals from this register are automatically evaluated.
For general information please refer to
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 0,2,3,4
10: Reserved (NT mode) or INFO 2 (TE mode)
11: Received INFO 3 (NT mode) or INFO 4 (TE mode)
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0:No illegal code violation is detected
1:Illegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0:No receive signal has been detected on the line.
1:Any receive signal has been detected on the line.
Data Sheet
7
TR_STA - Transceiver Status Register
RINF
H
SLIP
ICV
Chapter
191
0
3.5.
FSYN
Detailed Register Description
0
0
LD
PSB/PSF 21150
2003-01-30
IPAC-X
RD (33)