PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 179

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TIMR1
XCRC … Transmit CRC
0 … CRC is transmitted
1 … CRC isn’t transmitted
RCRC… Receive CRC
0 … CRC isn’t stored in the RFIFOD
1 … CRC is stored in the RFIFOD
ITF… Interframe Time Fill
Selects the inter-frame time fill signal which is transmitted between HDLC-frames.
0 … idle (continuous ’1’)
1 … flags (sequence of patterns: ‘0111 1110’)
Note: ITF must be set to ’0’ for power down mode.
4.1.9
Value after reset: 00
CNT ... Timer Counter
CNT together with VALUE determines the time period T after which a AUXI.TIN1
interrupt will be generated:
CNT=0...6:T = CNT x 2.048 sec + T1
CNT=7:T = T1 = ( VALUE+1 ) x 0.064 sec
The timer can be started by setting the STI-bit in CMDRD and will be stopped when a
TIN1 interrupt is generated or the TIMR1 register is written.
Note: If CNT is set to 7, a TIN interrupt is indefinitely generated after every expiration of
VALUE ... Timer Value
Determines the value of the timer value T1 = ( VALUE + 1 ) x 0.064 sec.
Data Sheet
In applications with D-channel access handling (collision resolution), the only
possible inter-frame time fill is idle (continuous ’1’). Otherwise the D-channel on
the S/T-bus cannot be accessed
T1 (i.e. T = T1).
7
TIMR1 - Timer 1 Register
CNT
H
5
4
179
(generated periodically)
with T1 = ( VALUE+1 ) x 0.064 sec
VALUE
Detailed Register Description
0
PSB/PSF 21150
RD/WR (24)
2003-01-30
IPAC-X