PSB21150FV14XT Infineon Technologies, PSB21150FV14XT Datasheet - Page 230

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Infineon Technologies

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

EXMB
MDS2-0
1
1
Note: - RAH1, RAH2: two programmable address values for the first received address
RAC ... Receiver Active
The B-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
4.6.6
Value after reset: 00
XFBS … Transmit FIFO Block Size
0 … Block size for the transmit FIFO data is 64 byte
1 … Block size for the transmit FIFO data is 32 byte
Note: A change of XFBS will take effect after a receiver command (CMDRB.XME,
Data Sheet
1
0
byte (in the case of an address field longer than 1 byte);
Group Address= fixed value FC / FE
- RAL1, RAL2: two programmable address values for the second (or the only, in
the case of a one-byte address) received address byte;
Group Address= fixed value FF
CMDRB.XRES, CMDRB.XTF) has been written.
1 Transparent
1 Transparent
7
Mode
mode 1
mode 2
EXMB - Extended Mode Register B-Channels
XFBS
H
RFBS
Number
of
Address
Bytes
> 1
> 1
SRA XCRC RCRC
1.Byte
RAH1,RAH2,
Group Address
–
H
.
230
H
Address Comparison
.
Detailed Register Description
2.Byte
–
RAL1,RAL2,
Group Address
0
0
ITF
PSB/PSF 21150
Remark
High-byte
address
compare.
Low-byte
address
compare.
2003-01-30
IPAC-X
RD/WR
(73/83)