MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 147
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MM912H634CV1AER2
Manufacturer Part Number
MM912H634CV1AER2
Description
64KS12 LIN2xLS/HS Isense
Manufacturer
Freescale Semiconductor
Series
-r
Datasheet
1.MM912G634CM1AE.pdf
(345 pages)
Specifications of MM912H634CV1AER2
Applications
Automotive
Core Processor
HCS12
Program Memory Type
FLASH (64 kB)
Controller Series
HCS12
Ram Size
6K x 8
Interface
LIN
Number Of I /o
-
Voltage - Supply
5.5 V ~ 27 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-LQFP Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4.26.1.2.3
Freescale Semiconductor
Note:
141.
Offset
IREFTR2…0
Reset
BGTRIMUP
BGTRIMDN
IREFTRE
W
R
CTR1_6
BGTRE
Field
(141)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
2-0
7
6
5
4
3
0xF2
Bandgap trim enable
Spare Trim Bit
Bandgap trim up bit
Bandgap trim down bit
Iref trim enable bit
Iref trim - This trim is used to adjust the internal zero TC current reference
7
0
0
Trimming Register 2 (CTR2)
0 - no trim can be done
1 - trim can be done by setting BGTRIMUP and BGTRIMDN bits
0 - default slope
1 - increase bandgap slope
0 - default slope
1 - decrease bandgap slope
0 - no trim can be done
1 - trim can be done by setting IREFTR[2:0] bits
000: 0%
001: +7.6%
010: +16.43%
011: +26.83%
100: -8.54%
101: -15.75%
110: -21.79%
111: 0%
6
0
0
Table 217. CTR1 - Register Field Descriptions
Table 218. Trimming Register 2 (CTR2)
MM912_634 Advance Information, Rev. 4.0
5
0
0
SLPBGTRE
4
0
Description
SLPBG_LOCK
3
0
SLPBGTR2
MM912_634 - Analog Die Trimming
2
0
SLPBGTR1
1
0
Access: User read/write
SLPBGTR0
0
0
147
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