MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 289

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the
parallel SPI data register after the last bit is shifted in.
After 2n SCK edges:
Figure 110
because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output
from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin
of the master must be either high or reconfigured as a general-purpose output not affecting the SPI.
Freescale Semiconductor
•
•
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
MOSI pin
MISO pin
Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was
in the data register of the slave is in the master.
The SPIF flag bit in SPISR is set indicating that the transfer is complete.
MSB first (LSBFE = 0):
t
t
t
LSB first (LSBFE = 1):
L
T
I
= Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram
= Minimum leading time before the first SCK edge, not required for back-to-back transfers
= Minimum trailing time after the last SCK edge
Figure 110. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width Selected (XFRW = 0)
t
L
1
MSB
LSB
2
3
Begin
Bit 6
Bit 1
4
MM912_634 Advance Information, Rev. 4.0
5
Bit 5
Bit 2
6
7
Bit 4
Bit 3
8
Transfer
9
Bit 3
Bit 4
10
11
Bit 2
Bit 5
12
13 14
Bit 1
Bit 6
End
15
MSB
LSB
16
t
T
Minimum 1/2 SCK
Begin of Idle State
t
I
for t
T
t
L
, t
l
, t
L
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