MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 218

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of
ARM.
4.32.4.3.4
In case of simultaneous matches the priority is resolved according to
possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described in
dictate that in the case of simultaneous matches, the match pointing to final state has highest priority followed by the lower
channel number (0,1,2).
4.32.4.4
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the trace buffer. Once
the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered.
Further transitions between the states are then controlled by the state control registers and channel matches. From Final State
the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each
transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches.
Independent of the state sequencer, each comparator channel can be individually configured to generate an immediate
breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an
immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If
a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0.
This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters
state0 and the debug module is disarmed.
4.32.4.4.1
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control as defined by the
TALIGN bit (see
the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon
completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to
Freescale Semiconductor
Priority
Highest
Lowest
State Sequence Control
Section 4.32.3.2.3, “Debug Trace Control Register
Channel Priorities
Final State
(Disarmed)
State 0
ARM = 0
Channel pointing to Final State
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
ARM = 0
Session Complete
Source
TRIG
(Disarm)
ARM = 1
ARM = 0
Figure 67. State Sequencer Diagram
MM912_634 Advance Information, Rev. 4.0
Table 323. Channel Priorities
Final State
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
Transition to next state as defined by state control registers
(DBGTCR)”). If the TSOURCE bit in DBGTCR is clear then
Table
State1
323. The lower priority is suppressed. It is thus
State3
Enter Final State
Action
State2
Table 323
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