MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 201

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.3.2.2
Read: Anytime
Write: Never
Freescale Semiconductor
Address: 0x0021
Reset
POR
DBGBRK
COMRV
W
R
Field
TRIG
ARM
BDM
1–0
7
6
4
3
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is
automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting
this bit the state sequencer enters State1.
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state sequencer
status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This
bit always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out.
If tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as defined
by the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing
session.
The session is ended by setting TRIG and ARM simultaneously.
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background Debug Mode
(BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module,
then breakpoints default to SWI.
S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint on reaching
the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing
is not enabled, the breakpoint is generated immediately.
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the 8-byte window
of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register
is visible at the address 0x0027. See
TBF
—
7
0
Debug Status Register (DBGSR)
0
1
0
1
0
1
0
1
COMRV
Debugger disarmed
Debugger armed
Do not trigger until the state sequencer enters the Final State.
Trigger immediately
Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
No Breakpoint generated
Breakpoint generated
00
01
10
11
6
0
0
0
= Unimplemented or Reserved
Visible Comparator
Table 273. Debug Status Register (DBGSR)
Comparator A
Comparator B
Comparator C
Table 271. DBGC1 Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
0
None
Table 272. COMRV Encoding
Table
272.
4
0
0
0
Description
Visible Register at 0x0027
3
0
0
0
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SSF2
2
0
0
SSF1
1
0
0
SSF0
0
0
0
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