DS32512N# Maxim Integrated Products, DS32512N# Datasheet - Page 38

• Manufacturer Part Number: DS32512N#
• Description: IC LIU DS3/E3/STS-1 484-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS32512N#

• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

8.5.2.1
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
resynchronization is initiated. Automatic pattern resynchronization can be disabled by setting BERT.CR:APRD = 1.
Pattern resynchronization can also be initiated manually by a zero-to-one transition of the Manual Pattern
Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted before comparison with the
receive pattern generator by setting BERT.CR:RPIC. See
Figure 8-8. PRBS Synchronization State Diagram
8.5.2.2
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern re-synchronization can be
disabled by setting BERT.CR:APRD = 1. Pattern resynchronization can also be initiated manually by a zero-to-one
transition of the Manual Pattern Resynchronization bit (BERT.CR:MPR). The incoming data stream can be inverted
before comparison with the receive pattern generator by setting BERT.CR:RPIC.
See
Figure 8-9
Receive PRBS Synchronization
Verify
Receive Repetitive Pattern Synchronization
for the repetitive pattern synchronization state diagram.
32 bits loaded
1 bit error
Sync
38 of 130
Load
Figure 8-8
for the PRBS synchronization diagram.
DS32506/DS32508/DS32512