DS32512N# Maxim Integrated Products, DS32512N# Datasheet - Page 87

• Manufacturer Part Number: DS32512N#
• Description: IC LIU DS3/E3/STS-1 484-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS32512N#

• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 5 to 3: Transmit Error Insertion Rate (TEIR[2:0]). This field indicates the rate at which errors are
automatically inserted in the output data stream. One out of every 10
of 0 disables error insertion. A value of 1 results in every 10th bit being inverted. A value of 2 result in every 100th
bit being inverted. Error insertion starts when this field is written with a non-zero value. If this field is written during
an error insertion, the new error rate is used after the next error is inserted. See Section 8.5.3.1.
Bit 2: Bit Error Insertion Enable (BEI). See Section 8.5.3.1.
Bit 1: Transmit Single Error Insert (TSEI). When BERT.TEICR:MEIMS = 0 and BEI = 1, this bit is used to insert
single-bit errors in the outgoing BERT data stream. A zero-to-one transition causes a single bit error to be inserted.
For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit
transitions more than once between error insertion opportunities, only one error is inserted. See Section
Bit 0: Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the error insertion signal for the
BERT block. Note: If TMEI or TSEI is one, changing the state of this bit may cause a bit error to be inserted. See
Section 8.7.5.
0 = single-bit error insertion is disabled
1 = single-bit error insertion is enabled
0 = error insertion is initiated by the BERT.TEICR:TSEI register bit
1 = error insertion is initiated by the transmit manual error insertion signal (TMEI) specified by the
PORT.CR1:MEIMS register bit.
15
—
—
0
7
0
14
—
—
0
6
0
BERT.TEICR
BERT Transmit Error Insertion Control Register
n * 80h + 58h
13
—
0
5
0
TEIR[2:0]
87 of 130
12
—
0
4
0
11
—
0
3
0
n
bits is inverted, where n = TEIR[2:0]. A value
BEI
10
—
0
2
0
DS32506/DS32508/DS32512
TSEI
—
9
0
1
0
MEIMS
8.7.5.
—
8
0
0
0