TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 283
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
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Price
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10.16.1.3
(1)
Transmit and Receive (Full-duplex)
SCLK Output Mode
・ If SCxMOD2<WBUF> is set to "0" and the double buffers are disabled
・ If SCxMOD2<WBUF> is set to "1" and the double buffers are enabled
Subsequently, 8 bits of data are shifted into receive buffer and the INTRXx receive interrupt
is generated. Concurrently, 8 bits of data written to the transmit buffer are outputted from the
TXD pin, the INTTXx transmit interrupt is generated when transmission of all data bits has
been completed. Then, the SCLK output stops.
receive buffer and the next transmit data is written to the transmit buffer by the CPU. The order
of reading the receive buffer and writing to the transmit buffer can be freely determined. Data
transmission is resumed only when both conditions are satisfied.
INTRXx interrupt is generated. While 8 bits of data is received, 8 bits of transmit data is
outputted from the TXD pin. When all data bits are sent out, the INTTXx interrupt is generated
and the next data is moved from the transmit buffer to the transmit shift register.
= 1) or when the receive buffer is full (SCxMOD2<RBFULL> = 1), the SCLK output is stop-
ped. When both conditions, receive data is read and transmit data is written, are satisfied, the
SCLK output is resumed and the next round of data transmission and reception is started.
SCLK is outputted when the CPU writes data to the transmit buffer.
The next round of data transmission and reception starts when the data is read from the
SCLK is outputted when the CPU writes data to the transmit buffer.
8 bits of data are shifted into the receive shift register, moved to the receive buffer, and the
If the transmit buffer has no data to be moved to the transmit buffer (SCxMOD2<TBEMP>
Page 263
TMPM330FDFG/FYFG/FWFG
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