TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 384

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

13.4
Operation Description
13.4.1.7
Remote control signal
waveform
Reversed remote control
signal waveform
(input from RXINx)
has low width.
enable the signal, it must be sent after being reversed by setting the RMCxRCR4 <RMCPO> bit to "1".
_ 0000,<RMCLCMAX[7:0]>><RMCLCMIN[7:0]>.
<RMCDATL[6:0]>.
RMCxRCR2, and configure the low-pulse width detection with <RMCLL[7:0]>.
receiving the last bit, receiving data is completed.
The figure shown below illustrates a remote control signal that starts with a leader of which waveform only
This signal starts with a leader that only has low width and a data bit cycle starts from the rising edge. To
This is because RMC is configured to detect a data bit cycle from the falling edge
To detect a leader, configure only low-pulse width of the leader with the <RMCLLMAX[7：0]>=0y0000
In this case, the value of <RMCLLMIN[7:0]> is set as "don't care".
To detect whether data "0" or data "1", configure the threshold of 0/1 detection with the RMCxRCR3
The maximum data bit cycle is configured with the <RMCDMAX[7:0]> of the RMCxRCR2.
To complete data reception, configure the maximum data bit cycle with <RMCDMAX[7:0]> of the
After detecting the maximum data bit cycle and confirming the low-pulse with which is specified after
The RMC generates an interrupt and waits for the next leader.
A Leader only with Low Width
Witing for a leader
Leader
Leader detection interrupt
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Detecting maximum data bit cycle completes reception.
Final bit
Low period
TMPM330FDFG/FYFG/FWFG
Low width detection interrupt
Waiting for a next leader