TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 343
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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Manufacturer
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12.3.9
31-23
22-20
19
18-16
15
14-12
11
10-8
7-1
0
After reset
After reset
After reset
After reset
bit symbol
bit symbol
bit symbol
bit symbol
Bit
−
CECWAV3[2:0]
−
CECWAV2[2:0]
−
CECWAV1[2:0]
−
CECWAV0[2:0]
−
CECWAVEN
CECRCR3 (Receive Control Register 3 )
Bit Symbol
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
Type
30
22
14
0
0
0
6
0
-
-
Read as 0.
The latest rising timing of logical "0" determined as proper waveform.
000: 56/fs (approx. 1.709 ms)
001: 56/fs + 1/fs
001: 56/fs + 2/fs
011: 56/fs + 3/fs
Read as 0.
The fastest rising timing of logical "0" deterrmined as proper.
000: 43/fs (approx.1.312 ms)
001: 43/fs − 1/fs
010: 43/fs − 2/fs
011: 43/fs − 3/fs
Read as 0.
The latest rising timing of logical "1" determined as proper waveform.
000: 26/fs (approx. 0.793 ms)
001: 26/fs + 1/fs
001: 26/fs + 2/fs
011: 26/fs + 3/fs
Read as 0
The fastest rising timing of logical "1" determined as proper.
000: 13/fs (approx. 0.396 ms)
001: 13/fs − 1/fs
010: 13/fs − 2/fs
011: 13/fs − 3/fs
Read as 0.
Waveform error detection
1: Enable
0: Disable
Detects a received waveform does not identical to the one defined and generates waveform error interrupt.
If enabled, an error is detected according to the setting of <CECWAV0> <CECWAV1> <CECWAV2>
<CEC WAV3>.
CECWAV3
CECWAV1
29
21
13
0
0
0
5
0
-
-
Page 323
28
20
12
0
0
0
4
0
-
-
27
19
11
0
0
0
3
0
-
-
-
-
Function
100: 56/fs + 4/fs
101: 56/fs + 5/fs
110: 56/fs + 6/fs
111: 56/fs + 7/fs
100: 43/fs − 4/fs
101: 43/fs − 5/fs
110: 43/fs − 6/fs
111: 43/fs − 7/fs
100: 26/fs + 4/fs
101: 26/fs + 5/fs
110: 26/fs + 6/fs
111: 26/fs + 7/fs
100: 13/fs − 4/fs
101: 13/fs − 5/fs
110: 13/fs − 6/fs
111: 13/fs − 7/fs
26
18
10
0
0
0
2
0
-
-
TMPM330FDFG/FYFG/FWFG
CECWAV2
CECWAV0
25
17
0
0
9
0
1
0
-
-
CECWAVEN
24
16
0
0
8
0
0
0
-
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