TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 355

• Manufacturer Part Number: TMPM330FWFG
• Description: Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
• Manufacturer: Toshiba

Specifications of TMPM330FWFG

• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 8K
• Number Of Pins: 100
• Package: LQFP(14×14)
• Vcc: 3V
• Cpu Mhz: 40
• Ssp (ch) Spi: -
• I2c/sio (ch): 3
• Uart/sio (ch): 3
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: -
• Cs/wait Controller (ch): -
• Dma Controller: -
• 10-bit Da Converter: -
• 10-bit Ad Converter: 12
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 10
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / Rohs Status: Details

(7)
(8)
(9)
0 ms
Permissible value of signal transition timing on specification (Start bit)
<CECRIHLD>, is valid.
does not correspond with the address set in the CECADD register.
an ACK response of neither the header block nor the data block is sent.
bit detection respectively.
start bit rising timing (1. in the figure shown below).
maximum cycle of a start bit (2. in the figure shown below).
is considered to be valid.
Note 1: A broadcast message is received regardless of the <CECOTH> register setting.
Note 2: If the initiator sends a new message beginning with the start bit without having sent the last block
Configure the CECRCR1<CECTOUT> bit to specify the time to determine a timeout.
This is used when the setting of a receive error interrupt suspension, which is specified in CECRCR1
By setting CECRCR1 <CECOTH>, you can specify if data is received or not when destination address
In this case, data is received as usual, and an interrupt is generated by detecting an error. However,
Configuring the CECRCR2 register allows you to specify the rising timing and a cycle of the start
<CECSWAV0> is to specify the fastest start bit rising timing. <CECSWAV1> is to specify the latest
<CECSWAV2> is to specify the minimum cycle of a start bit. <CECSWAV3> is to specify the
If a rising edge during the period 1. and a falling edge during the period 2. are detected, the start bit
Cycles to Identify Timeout
Data Reception at Logical Address Discrepancy
Start Bit Detection
with EOM="1", a maximum cycle error is determined for the ACK bit and an interrupt is generated.
Then, the receive operation is performed in the usual way.
<CECSWAV0>
115/fs ~ 115/fs - 7/fs
(approx.3.510ms)
3.5 ms
<CECSWAV1>
128/fs ~ 128/fs + 7/fs
(approx.3.906ms)
Page 335
1.
3.7 ms
<CECSWAV2>
141/fs - 7/fs ~ 141/fs
(approx.4.303ms)
4.3 ms
2.
TMPM330FDFG/FYFG/FWFG
<CECSWAV3>
154/fs ~ 154/fs + 7/fs
(approx.4.700ms)
4.7 ms