TMPM330FWFG Toshiba, TMPM330FWFG Datasheet
TMPM330FWFG
Specifications of TMPM330FWFG
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TMPM330FWFG Summary of contents
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... TX System RISC TX03 Series TMPM330FDFG TMPM330FYFG TMPM330FWFG Tentative Semiconductor Company ...
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Date Revision 2009/6/25 Tentative 1 Revision History First Release ...
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... Pin Functions.............................................................................................................. 23 4.5 Connection with a Debug Tool.................................................................................. 24 5 Memory Map ....................................................................................................................... 25 5.1 Memory Map of the TMPM330FDFG......................................................................... 26 5.2 Memory Map of the TMPM330FYFG ......................................................................... 27 5.3 Memory Map of the TMPM330FWFG ........................................................................ 28 6 Reset ................................................................................................................................... 29 6.1 Cold Reset................................................................................................................... 29 6.2 Warm Reset................................................................................................................. 30 6.2.1 Reset Period.............................................................................................................. 30 6.2.2 After Reset ................................................................................................................. 30 7 Clock/Mode Control........................................................................................................... 31 7 ...
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Registers ..................................................................................................................... 32 7.2.1 Register List ........................................................................................................ 32 7.2.2 Detailed Description of Registers ..................................................................... 33 7.3 Clock Control.............................................................................................................. 38 7.3.1 Clock System Block Diagram............................................................................ 38 7.3.2 Initial Values after Reset .................................................................................... 38 7.3.3 Clock Multiplication Circuit (PLL)..................................................................... 40 7.3.4 ...
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Register List ........................................................................................................ 73 8.6.2 NVIC Registers.................................................................................................... 74 8.6.3 NVIC Registers.................................................................................................... 96 9 Input/Output Ports ........................................................................................................... 103 9.1 Port registers ............................................................................................................ 103 9.2 Port Functions .......................................................................................................... 104 9.2.1 Port States in STOP Mode ............................................................................... 104 9.2.2 Precaution for Mode ...
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Type T16 ............................................................................................................ 142 9.3.18 Type T17 ............................................................................................................ 143 9.3.19 Type T18 ............................................................................................................ 144 10 16-bit Timer/Event Counters (TMRBs) ....................................................................... 145 10.1 Outline ....................................................................................................................... 145 10.2 Differences in the Specifications............................................................................ 146 10.3 Configuration............................................................................................................ 148 10.4 Registers ................................................................................................................... 150 10.4.1 ...
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Receive FIFO Buffer ......................................................................................... 194 11.3.8 Receive FIFO Operation................................................................................... 194 11.3.9 Transmit Counter.............................................................................................. 196 11.3.10 Transmit Control Unit ................................................................................... 196 11.3.11 Transmit Buffer ............................................................................................. 198 11.3.12 Transmit FIFO Buffer .................................................................................... 199 11.3.13 Transmit FIFO Operation.............................................................................. 199 11.3.14 Parity Control ...
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Control....................................................................................................................... 233 12.3 I2C Bus Mode Data Formats.................................................................................... 234 12.4 Control Registers in the I2C Bus Mode ................................................................. 235 12.5 Control in the I2C Bus Mode ................................................................................... 244 12.5.1 Setting the Acknowledgement Mode.............................................................. 244 12.5.2 Setting the Number of ...
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CEC Enable Register [CECEN]........................................................................ 275 13.2.3 Logical Address Register [CECADD] ............................................................. 275 13.2.4 Software Reset Register [CECRESET] ........................................................... 276 13.2.5 Receive Enable Register [CECREN] ............................................................... 276 13.2.6 Receive Buffer Register [CECRBUF].............................................................. 277 13.2.7 Receive Control Register 1 [CECRCR1]......................................................... 278 ...
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Registers ................................................................................................................... 334 15.2 Registers Description .............................................................................................. 335 15.3 Conversion Clock..................................................................................................... 347 15.4 Description of Operations ....................................................................................... 348 15.4.1 Analog Reference Voltage ............................................................................... 348 15.4.2 Selecting the Analog Input Channel ............................................................... 348 15.4.3 Starting A/D Conversion .................................................................................. 349 15.4.4 ...
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Reset Operation................................................................................................ 382 18.2.2 User Boot Mode (Single chip mode)............................................................... 383 18.2.3 Single Boot Mode ............................................................................................. 390 18.3 On-board Programming of Flash Memory (Rewrite/Erase) ................................. 420 18.3.1 Flash Memory ................................................................................................... 420 19 ROM protection ............................................................................................................ 439 19.1 Outline ....................................................................................................................... ...
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Package......................................................................................................................... 483 RESTRICTIONS ON PRODUCT USE...................................................................................... 485 x ...
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ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. **************************************************************************************************************** Under development ...
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... Optimized design using a low power consumption library • Standby function that stops the operation of the microcontroller core 3) High-speed interrupt response suitable for real-time control • An interruptible long instruction. • Stack push automatically handled by hardware. Under development TMPM330FDFG TMPM330FYFG TMPM330FWFG Page2 TMPM330 TM -M3 microcontroller ® -2 instruction ...
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... On Chip program memory and data memory Product name TMPM330FDFG TMPM330FYFG TMPM330FWFG (3) 16-bit timer • 16-bit interval timer mode • 16-bit event counter mode • 16-bit PPG output • Input capture function (4) Real time clock (RTC) • Clock (hour, minute and second) • ...
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Overview and Features (13) Standby mode • Standby modes • Sub clock operation(32.768kHz) (14) Clock generator • On-chip PLL (quadrupled) • Clock gear function: The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. (15) Endian • ...
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Block Diagram Cortex-M3 CPU Debug NVIC CG SIO (3ch) I2C (3ch) CEC Remote control signal preprocessor (2ch) Fig. 1-1 TMPM330 FDFG/FYFG/FWFG Block Diagram Under development FLASH I/F I-Code D-Code RAM I/F System BOOT I/F ROM Bus Bridge PORT 0~A ...
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Overview and Features Under development Page6 TMPM330 ...
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... Pin Layout and Pin Functions This chapter describes the pin layout, pin names and pin functions of TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG. 2.1 Pin Layout (Top view) Fig.2-1 shows the pin layout of TMPM330FDFG/TMPM330FYFG/TMPM330FWF. AN10/ PD6 AN11/ PD7 AVSS VREFH AVCC 5 INT4/ PG3 TB9OUT/ PK2 ...
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Pin Layout and Pin Functions Pin Pin name No. 1 PD6, AN10 2 PD7, AN11 3 AVSS VREFH 4 5 AVCC 6 PG3, INT4 7 PK2, TB9OUT 8 PJ5, TB7OUT 9 PH4, TB2IN0 10 PH5, TB2IN1 PG7, TB8OUT 11 ...
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Pin Pin name No. 51 PK1, SCOUT, ALARM PI4, TB4OUT 52 53 PI5, TB5OUT 54 PB0, TDO, SWV PA0, TMS, SWDIO 55 56 PA1, TCK, SWCLK 57 TEST3 58 PJ7, INT7 59 PB1, TDI 60 PB2, TRST 61 PF3, RXIN1 ...
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... Pin names and Functions Table2-2 and Table2-3 sort the input and output pins of the TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG by pin or port. Each table includes alternate pin names and functions for multi-function pins. 2.2.1 Sorted by Pin Table2-2 Pin Names and Functions Sorted by Pin (1/5) ...
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Table2-2 Pin Names and Functions Sorted by Pin (2/ Input/ Type Pin Name Pins Output PE0 I/O 20 TXD0 O PE1 I/O 21 RXD0 I PE2 I/O 22 SCLK0 I CTS0 I PE4 I/O 23 TXD1 O PE5 ...
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Pin Layout and Pin Functions Table2-2 Pin Names and Functions Sorted by Pin (3/ Input/ Type Pin Name Pins Output PI1 I/O 40 TB1OUT O 41 PB5 I/O PI2 I/O 42 TB2OUT O 43 PB6 I/O PF4 ...
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Table2-2 Pin Names and Functions Sorted by Pin (4/ Input/ Type Pin Name Pins Output PA2 I TRACECLK PA3 I TRACEDATA0 Function/ PA4 I Debug TRACEDATA1 PA5 I TRACEDATA2 PA6 ...
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Pin Layout and Pin Functions Table2-2 Pin Names and Functions Sorted by Pin (5/ Input/ Type Pin Name Pins Output PC0 I 91 AN0 I PC1 I 92 AN1 I PC2 I 93 AN2 I PC3 I ...
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Sorted by Port Table2-3 Pin Names and Functions Sorted by Port (1/ Type Pin Pin Name PA0 55 TMS/SWDIO PA1 56 TCK/SWCLK PA2 64 TRACECLK Function PA3 65 / TRACEDATA0 A Debug ...
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Pin Layout and Pin Functions Table2-3 Pin Names and Functions Sorted by Port (2/ Type Pin Name Pin PD3 I 98 AN7 I TB6IN1 I PD4 I 99 AN8 I PD5 I ...
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Table2-3 Pin Names and Functions Sorted by Port (3/ Input Type Pin Name R Pin Output T s PG0 I/O 26 SDA0/ I/O SO0 O PG1 I/O 27 SCL0/ I/O SI0 I PG2 I/O SCK0 I/O ...
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Pin Layout and Pin Functions Table2-3 Pin Names and Functions Sorted by Port Number (4/ Input/ O Type Pin Name Pin R Output s T PI0 I/O 38 TB0OUT O PI1 I/O 40 TB1OUT O PI2 ...
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Table2-3 Pin Names and Functions Sorted by Port (5/5) Input Type Pin Name Pins Output 82 I RESET Function 80 I NMI Control 81 MODE Clock 77 XT1 I 78 XT2 ...
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Pin Layout and Pin Functions 2.3 Pin Names and Power Supply Pins 2.4 Pin Numbers and Power Supply Pins Power supply DVCC AVCC REGVCC CVCC development Under Table2-4 Pin Names and Power Supplies Power Pin name supply PA DVCC ...
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... ARM Limited. Product Name TMPM330FDFG TMPM330FYFG TMPM330FWFG The Cortex-M3 core has the optional blocks. The optional blocks of the revision r1p1 are ETM and MPU. Not MPU but ETM is contained in the TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG. Under development Core Revision r1p1-00rel0 r1p1-01rel0 Page21 ...
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Processor Core and Memory Map Under development Page22 TMPM330 ...
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Debug Interface 4.1 Specification Overview The TMPM330 contains the Serial Wire JTAG Debug Port (SWJ-DP) unit for interfacing with the In-Circuit Emulator (ICE) and the Embedded Trace Macrocell output. Trace data is output to the dedicated pins (TRACEDATA[0]-[3], SWV) ...
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Debug Interface The table below summarizes the debug interface pin functions and related port settings after reset. Pin Port Number (Bit Name) 55 PA0 56 PA1 54 PB0 59 PB1 60 PB2 64 PA2 65 PA3 66 PA4 67 ...
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... Memory Map The memory maps for the TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG are based on the ARM Cortex-M3 processor core memory map. The internal ROM, internal RAM and internal I/O of the TMPM330FDFG/ TMPM330FYFG/ TMPM330FWFG are mapped to the code, SRAM and peripheral regions of the Cortex-M3 respectively. The SRAM and internal I/O regions are all included in the bit-band region. The CPU register region is the processor core’ ...
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Memory Map 5.1 Memory Map of the TMPM330FDFG Fig 5-1 shows the memory map of the TMPM330FDFG. Under development 0xFFFF FFFF Vencor-Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0xDFFF FFFF Fault 0x4007 FFFF Internal IO 0x4000 ...
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Memory Map of the TMPM330FYFG Fig. 5-2 shows the memory map of the TMPM330FYFG. (Note) In addition to 256KB flash area, the TMPM330FYFG provides 128-word data/ password area (1 page) for Show Product Information command in the address range ...
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... Memory Map 5.3 Memory Map of the TMPM330FWFG Fig. 5-3 shows the memory map of the TMPM330FWFG. Under development 0xFFFF FFFF Vendor-Specific 0xE010 0000 0xE00F FFFF CPU Register Region 0xE000 0000 0xDFFF FFFF Fault 0x4007 FFFF Internal IO 0x4000 0000 Fault 0x2000 1FFF Internal RAM (8K) ...
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Reset The TMPM330 has three reset sources: an external reset pin, WDT and SYSRESETREQ. For reset from the WDT, refer to the chapter on the WDT. For reset from SYSRESETREQ, refer to “Cortex-M3 Technical Reference Manual”. 6.1 Cold Reset ...
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Reset 6.2 Warm Reset 6.2.1 Reset Period As a precondition, ensure that the power supply voltage is within the operating range and the internal high-frequency oscillator is providing stable oscillation. To reset the TMPM330, assert the RESET signal (active ...
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Clock/Mode Control 7.1 Features The clock/mode control block enables to select clock gear, prescaler clock and warm-up of the PLL (including clock multiplication circuit) and oscillator. The low power consumption mode can reduce power consumption. This chapter describes how ...
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Clock/Mode Control 7.2 Registers 7.2.1 Register List Table 7-1 shows registers and addresses of the clock generator. System control register 0 System control register 1 System control register 2 Oscillation control register 0 Oscillation control register 1 Standby control ...
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Detailed Description of Registers 7.2.2.1 System Control Register 7 Bit symbol - SYSCR0 Read/Write After reset 0 Function 15 Bit symbol - SYSCR1 Read/Write After reset 0 Function 23 Bit symbol - SYSCR2 Read/Write After reset 0 Function 31 ...
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Clock/Mode Control 7.2.2.2 Oscillation Control Register 7 Bit symbol - OSCCR0 Read/Write R After reset 0 Function “0” is read. 15 Bit symbol - OSCCR1 Read/Write After reset 0 Function “0” is read. 23 Bit symbol - Read/Write After ...
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Standby Control Register 7 Bit symbol - STBYCR0 Read/Write After reset 0 Function 15 Bit symbol - STBYCR1 Read/Write After reset 0 Function 23 Bit symbol - STBYCR2 Read/Write After reset 0 Function 31 Bit symbol - Read/Write After ...
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Clock/Mode Control 7.2.2.4 PLL Selection Register 7 Bit symbol - PLLSEL Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol - Read/Write ...
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System Clock Selection Register 7 Bit symbol - CKSEL Read/Write After reset 0 Function 15 Bit symbol - Read/Write After reset 0 Function 23 Bit symbol - Read/Write After reset 0 Function 31 Bit symbol - Read/Write After reset ...
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Clock/Mode Control 7.3 Clock Control 7.3.1 Clock System Block Diagram Fig.7-1 shows the clock system diagram. Each clock is defined as follows. fosc : Clock input from the X1 and X2 pins fs : Clock input from the XT1 ...
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OSCCR0<WUEON> OSCCR0<WUPT2:0> Warp-up timer OSCCR0 <WUPSEL> OSCCR1 <XEN> Starts oscillation after reset X1 High-speed PLL oscillator X2 fosc OSCCR0 <PLLON> Stops after releasing reset XT1 Low-speed oscillator XT2 fs OSCCR1 <XTEN> Starts oscillation after reset. fperiph 1/2 1/4 1/8 1/16 ...
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Clock/Mode Control 7.3.3 Clock Multiplication Circuit (PLL) This circuit outputs the fpll clock that is quadruple of the high-speed oscillator output clock, fosc. This lowers the oscillator input frequency while increasing the internal clock speed. The PLL is disabled ...
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Table 7-2 Warm-up Time (fosc=10 MHz, fs=32.768 kHz) Warm-up time options OSCCR0<WUPT 2:0> 000 001 010 011 100 101 110 111 (Note) The warm-up timer operates according to the oscillation clock, and it may contain errors if there is any ...
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Clock/Mode Control 7.3.5 System Clock The TMPM330 offers two selectable system clocks: low-speed or high-speed. The high-speed clock is dividable. • Input frequency from X1 and X2: 8MHz~10MH • Allows for oscillator connection or external clock input. • Clock ...
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System Clock Pin Output Function The TMPM330 enables to output the system clock from a pin. The PK1/SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral ...
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Clock/Mode Control 7.4 Modes and Mode Transitions 7.4.1 Mode Transitions The NORMAL mode and the SLOW mode use the high-speed and low-speed clocks for system clock respectively. The IDLE, SLEEP and STOP modes can be used as the low ...
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Operation Modes Two operation modes, NORMAL and SLOW, are available. The features of each mode are described below. 7.5.1 NORMAL Mode This mode is to operate the CPU core and the peripheral hardware by using the high-speed clock. It ...
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Clock/Mode Control 7.6.1 IDLE Mode Only the CPU is stopped in this mode. Each peripheral function has one bit in its control register for enabling or disabling operation in the IDLE mode. When the IDLE mode is entered, peripheral ...
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Pin Name X1, XT1 Not X2, XT2 Ports RESET, NMI, MODE PA0, PB0 [When used as a debug pin (PxFR<n>=1) and output is enabled (PxCR<n>=1)] PF7, PG3, PJ0-3, PJ6, PJ7 Ports [When used as an interrupt pin (PxFR<n>=1) and input ...
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Clock/Mode Control 7.6.4 Low power Consumption Mode Setting The low power consumption mode is specified by the setting of the standby control register STBYCR<STBY2:0>. Table 7-7 shows the mode setting in the <STBY2:0>. Table 7-7 Low power consumption mode ...
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Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, NMI or reset. The release source that can be used is determined by the low power consumption mode selected. Details are ...
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Clock/Mode Control 7.6.7 Warm-up Mode transition may require the warm-up so that the internal oscillator provides stable oscillation. In the mode transition from STOP to NORMAL/ SLOW or from SLEEP to NORMAL, the warm-up counter is activated automatically. And ...
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Clock Operations in Mode Transition The clock operations in mode transition are described in the following sections 7.6.8.1 to 7.6.8.4. 7.6.8.1 Transition of operation modes: NORMAL→STOP→NORMAL When returning to NORMAL mode from STOP mode, the warm-up is activated automatically. ...
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Clock/Mode Control 7.6.8.3 Transition of operation modes: SLOW→STOP→SLOW The warm-up is activated automatically necessary to set the warm-up time before entering the STOP mode. WFI instruction / sleep-on-exit SLOW Mode fs Warm-up fsys (System clock = fs) ...
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Exceptions This chapter describes features, types and handling of exceptions. Exceptions have close relation to the CPU core. Refer to “Cortex-M3 Technical Reference Manual” if needed. 8.1 Overview An exception causes the CPU to stop the currently executing process ...
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Exceptions 8.1.2 Handling Flowchart The following shows how an exception/interrupt is handled. indicates hardware handling. Each step is described later in this chapter. Processing Detection by CG/CPU Handling by CPU Branch to ISR Execution of ISR Return from exception ...
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Exception Request and Detection (1) Exception occurrence Exception sources include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception occurs when the CPU executes an instruction that causes an ...
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Exceptions (Note 1) This product does not contain the MPU. (Note 2) External interrupts have different sources and numbers in each product. For details, see “List of Interrupt Sources”. (3) Priority setting Use the Interrupt Priority Registers to assign ...
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Exception Handling and Branch to the Interrupt Service Routine (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called “pre-emption”. (1) Stacking When the CPU detects an ...
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Exceptions (3) Late-arriving If the CPU detects a higher priority exception before executing the ISR for a previous exception, the CPU handles the higher priority exception first. This is called “late-arriving”. A late-arriving exception causes the CPU to fetch ...
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Executing an ISR An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the user. An ISR may need to include code for clearing the interrupt request so that the same interrupt will not occur ...
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Exceptions 8.2 Reset Exceptions Reset exceptions are generated from the following three sources. Use the Reset Flag (RSTFLG) Register of the Clock Generator to identify the source of a reset. ・External reset pin A reset exception occurs when an ...
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SysTick SysTick provides interrupt features using the CPU’s system timer. When you set a value in the SysTick Reload Value Register and enable the SysTick features in the SysTick Control and Status Register, the counter loads with the value ...
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Exceptions 8.5 Interrupts This chapter describes routes, sources and required settings of interrupts. The CPU is notified of interrupt requests by the interrupt signal from each interrupt source. It sets priority on interrupts and handles an interrupt request with ...
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Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC’s Interrupt Set-Pending Register. ・From external pin Set the port control register so that the external pin ...
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Exceptions 8.5.1.4 List of Interrupt Sources Table 8-2 shows the list of interrupt sources. Table 8-2 List of Hardware Interrupt Sources (1/2) No. INT0 0 INT1 1 INT2 2 INT3 3 INT4 4 INT5 5 INTRX0 6 INTTX0 7 ...
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Table 8-2 List of Hardware Interrupt Sources (2/2) No. Interrupt Sources INTCAP20 43 16bit TMRB input capture 20 INTCAP21 44 16bit TMRB input capture 21 INTCAP30 45 16bit TMRB input capture 30 INTCAP31 46 16bit TMRB input capture 31 INTCAP40 ...
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Exceptions 8.5.2 Interrupt Handling 8.5.2.1 Flowchart The following shows how an interrupt is handled. indicates hardware handling. Processing Settings for detection Settings for sending interrupt signal Interrupt generation Not clearing standby mode Clearing standby mode CG detects interrupt (clearing ...
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Processing The CPU detects the interrupt. CPU detects interrupt The CPU handles the interrupt. CPU handles interrupt The CPU pushes register contents to the stack before entering the ISR. Program for the ISR. ISR execution Clear the interrupt source if ...
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Exceptions 8.5.2.2 Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following ...
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CPU registers setting You can assign a priority level to each interrupt source in the corresponding Interrupt Priority Register of the NVIC. Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, ...
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Exceptions (6) Configuring the clock generator For an interrupt source to be used for clearing a standby mode, you need to set the active state and enable interrupts in the IMCG register of the clock generator. The IMCG register ...
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Detection by Clock Generator If an interrupt source is used for clearing a standby mode, an interrupt request is detected according to the active level specified in the clock generator, and is notified to the CPU. An edge-triggered interrupt ...
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Exceptions 8.5.2.6 Interrupt Service Routine (ISR) An ISR requires specific programming according to the application to be used. This section describes what is recommended at the service routine programming and how the source is cleared. (1) Pushing during ISR ...
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Exception/Interrupt-Related Registers The CPU’s NVIC registers and clock generator registers described in this chapter are shown below with their respective addresses. 8.6.1 Register List ●NVIC registers SysTick Control and Status Register SysTick Reload Value Register SysTick Current Value Register ...
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Exceptions 8.6.2 NVIC Registers 8.6.2.1 SysTick Control and Status Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit0> ...
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SysTick Reload Value Register 7 bit Symbol Read/Write After reset Function 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function <bit23:0> <RELOAD> Set the value to load ...
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Exceptions 8.6.2.3 SysTick Current Value Register 7 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 15 bit Symbol Read/Write After reset Function [Read] Current SysTick timer value [Write] Clear 23 bit Symbol Read/Write After ...
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SysTick Calibration Value Register 7 bit Symbol Read/Write After reset 1 Function 15 bit Symbol Read/Write After reset 0 Function 23 bit Symbol Read/Write After reset 0 Function 31 bit Symbol NOREF Read/Write RR After reset 0 Function 0: ...
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Exceptions 8.6.2.5 Interrupt Set-Enable Register 1 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Enable ...
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Interrupt Set-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Enable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Enable [Read] 0: ...
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Exceptions 8.6.2.7 Interrupt Clear-Enable Register 7 bit Symbol Read/Write After reset 0 Function Interrupt number 7 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 15 [Write] 1: Disable [Read] ...
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Interrupt Clear-Enable Register 2 7 bit Symbol Read/Write After reset 0 Function Interrupt number 39 [Write] 1: Disable [Read] 0: Disabled 1: Enabled 15 bit Symbol Read/Write After reset 0 Function Interrupt number 47 [Write] 1: Disable [Read] 0: ...
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Exceptions 8.6.2.9 Interrupt Set-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt number 7 [Write] 1: Pend [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function Interrupt number 15 [Write] 1: Pend [Read] ...
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Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on an interrupt ...
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Exceptions 8.6.2.10 Interrupt Set-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt number 39 [Write] 1: Pend [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function Interrupt number 47 [Write] 1: Pend [Read] ...
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Use these bits to force interrupts into the pending state or determine which interrupts are currently pending. Writing “1” bit in this register pends the corresponding interrupt. However, writing “1” has no effect on an interrupt ...
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Exceptions 8.6.2.11 Interrupt Clear-Pending Register 1 7 bit Symbol Read/Write After reset Function Interrupt number 7 [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function Interrupt number 15 [Write] 1: ...
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Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt that is ...
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Exceptions 8.6.2.12 Interrupt Clear-Pending Register 2 7 bit Symbol Read/Write After reset Function Interrupt number 39 [Write] 1: Clear pending interrupt [Read] 0: Not pending 1: Pending 15 bit Symbol Read/Write After reset Function Interrupt number 47 [Write] 1: ...
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Use these bits to clear pending interrupts or determine which interrupts are currently pending. Writing “1” bit in this register clears the corresponding pending interrupt. However, writing “1” has no effect on an interrupt that is ...
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Exceptions 8.6.2.13 Interrupt Priority Registers Each interrupt is provided with eight bits of an Interrupt Priority Register. The following shows the addresses of the Interrupt Priority Registers corresponding to interrupt numbers. 31 0xE000_E400 PRI_3 0xE000_E404 PRI_7 0xE000_E408 PRI_11 0xE000_E40C ...
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Priority of interrupt number 0 Priority of interrupt number 1 <bit15:13> <PRI_1> <bit23:21> <PRI_2> Priority of interrupt number 2 Priority of interrupt number 3 <bit31:29> <PRI_3> Under development Page91 TMPM330 ...
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Exceptions 8.6.2.14 Vector Table Offset Register 7 bit Symbol TBLOFF Read/Write R/W After reset 0 Function Offset value 15 bit Symbol Read/Write After reset Function 23 bit Symbol Read/Write After reset Function 31 bit Symbol Read/Write After reset Function ...
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System Handler Priority Registers Each exception is provided with eight bits of a System Handler Priority Register. The following shows the addresses of the System Handler Priority Registers corresponding to each exception. 31 0xE000_ED18 PRI_7 0xE000_ED1C PRI_11 (SVCall) 0xE000_ED20 ...
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Exceptions 8.6.2.16 System Handler Control and State Register 7 bit Symbol SVCALL ACT Read/Write R/W After reset 0 Function SVCall 0: Inactive 1: Active 15 bit Symbol SVCALL PENDED Read/Write R/W After reset 0 Function SVCall 0: Not pended ...
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You must clear or set the active bits with extreme caution ...
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Exceptions 8.6.3 NVIC Registers 8.6.3.1 CG Interrupt Mode Control Register A 7 IMCGA bit Symbol Read/Write R After reset 0 “0” is read. Active state setting of INT0 standby Function 15 bit Symbol Read/Write R After reset 0 “0” ...
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CG Interrupt Mode Control Register B 7 IMCGB bit Symbol Read/Write R After reset 0 Function “0” is read. Active state setting of INT4 standby 15 bit Symbol Read/Write R After reset 0 “0” is read. Active state setting ...
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Exceptions 8.6.3.3 CG Interrupt Mode Control Register C 7 IMCGC bit Symbol Read/Write R After reset 0 “0” is read. Active state setting of INTRTC Function 15 bit Symbol Read/Write R After reset 0 Function “0” is read. Active ...
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CG Interrupt Mode Control Register D 7 IMCGD bit Symbol Read/Write R After reset 0 “0” is read. Active state setting of INTCECTX Function 15 bit Symbol Read/Write R After reset 0 Function “0” is read. 23 bit Symbol ...
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Exceptions 8.6.3.5 CG Interrupt Request Clear Register ICRCG bit Symbol Read/Write After reset Function “0” is read. bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function Under development 7 6 ...
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NMI Flag Register NMIFLG 7 bit Symbol Read/Write After reset 0 Function 15 bit Symbol Read/Write After reset 0 Function 23 bit Symbol Read/Write After reset 0 Function 31 bit Symbol Read/Write After reset 0 Function (Note) <NMIFLG1:0> are ...
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Exceptions 8.6.3.7 Reset Flag Register RSTFLG bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function bit Symbol Read/Write After reset Function (Note 1) The TMPM330 has power-on reset circuit and ...
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Input/Output Ports 9.1 Port registers Px : Port register To read/ write port data. PxCR : Control register To control input/output * Need to enable the input with PxIE register even when input is set. PxFRn : Function register ...
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Input/Output Ports 9.2 Port Functions 9.2.1 Port States in STOP Mode Input and output in STOP mode are enabled/disabled by the STBYCR2<DRVE> bit in the Standby Control Register. If PxIE or PxCR is enabled with <DRVE>=1, input or output ...
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Under development Page105 TMPM330 ...
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Input/Output Ports 9.2.3 Port A (PA0~PA7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port A performs the debug ...
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T1 Type 7 PA7 PA Bit Symbol (0x4000_0000) Read/Write After reset 7 PA7C PACR Bit Symbol (0x4000_0004) Read/Write After reset 0 Function 7 － PAFR1 Bit Symbol (0x4000_0008) Read/Write R After reset 0 Function “0” is read. 7 PA7UP ...
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Input/Output Ports 9.2.4 Port B (PB0~PB7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose input/output function, the port B performs the debug ...
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T1 Type 7 PB7 PB Bit Symbol (0x4000_0040) Read/Write After reset 7 PB7C PBCR Bit Symbol (0x4000_0044) Read/Write After reset 0 Function 7 － PBFR1 Bit Symbol (0x4000_0048) Read/Write After reset Function 7 PB7UP PBPUP Bit Symbol (0x4000_006C) Read/Write ...
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Input/Output Ports 9.2.5 Port C (PC0~PC3) The port 4-bit input port. Besides the general-purpose input function, the port C functions as analog input pins of the A/D converter. Reset initializes all bits of the port C ...
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Port D (PD0~PD7) The port 8-bit input port. Besides the general-purpose input function, the port D receives an analog input of the A/D converter and a 16-bit timer input. Reset initializes all bits of the port ...
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Input/Output Ports 9.2.7 Port E (PE0~PE6) The port general-purpose, 7-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port E performs the serial ...
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PECR Bit Symbol (0x4000_0104) Read/Write R After reset 0 Function “0” is read. 7 － PEFR1 Bit Symbol (0x4000_0108) Read/Write R After reset 0 Function “0” is read. 7 － PEFR2 Bit Symbol (0x4000_010C) Read/Write R After reset ...
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Input/Output Ports 9.2.8 Port F (PF0~PF7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port F performs the functions ...
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PF7C PFCR Bit Symbol (0x4000_0144) Read/Write After reset 0 Function 7 PF7F1 PFFR1 Bit Symbol (0x4000_0148) Read/Write After reset 0 Function 0:PORT 1: INT5 7 － PFFR2 Bit Symbol (0x4000_014C) Read/Write After reset Function 7 PF7OD PFOD Bit Symbol ...
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Input/Output Ports 9.2.9 Port G (PG0~PG7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port G performs the functions ...
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T10 Type 7 PG7 PG Bit Symbol (0x4000_0180) Read/Write After reset 7 PG7C PGCR Bit Symbol (0x4000_0184) Read/Write After reset 0 Function 7 PG7F1 PGFR1 Bit Symbol (0x4000_0188) Read/Write After reset 0 Function 0:PORT 1: TB8OUT 7 PG7OD PGOD ...
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Input/Output Ports 9.2.10 Port H (PH0~PH7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port H performs the functions ...
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T3 Type 7 PH7 PH Bit Symbol (0x4000_01C0) Read/Write After reset 7 PH7C PHCR Bit Symbol (0x4000_01C4) Read/Write After reset 0 Function 7 PH7F1 PHFR1 Bit Symbol (0x4000_01C8) Read/Write After reset 0 Function 0:PORT 1: TB3IN1 7 PH7UP PHPUP ...
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Input/Output Ports 9.2.11 Port I (PI0~PI7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port I performs the 16-bit ...
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Under development Page121 TMPM330 ...
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Input/Output Ports 9.2.12 Port J (PJ0~PJ7) The port general-purpose, 8-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port J performs the functions ...
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T7 Type 7 PJ7 PJ Bit Symbol (0x4000_0240) Read/Write After reset 7 PJ7C PJCR Bit Symbol (0x4000_0244) Read/Write After reset 0 Function 7 PJ7F1 PJFR1 Bit Symbol (0x4000_0248) Read/Write After reset 0 Function 0:PORT 1: INT7 7 PJ7UP PJPUP ...
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Input/Output Ports 9.2.13 Port K (PK0~PK2) The port general-purpose, 3-bit input/output port. For this port, inputs and outputs can be specified in units of bits. Besides the general-purpose port function, the port K performs the functions ...
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Type 7 － PK Bit Symbol (0x4000_0280) Read/Write After reset 7 － PKCR Bit Symbol (0x4000_0284) Read/Write After reset Function 7 － PKFR1 Bit Symbol (0x4000_0288) Read/Write After reset Function 7 － PKFR2 Bit Symbol (0x4000_028C) Read/Write After ...
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Input/Output Ports 9.3 Block Diagrams of Ports 9.3.1 Port Types The ports are classified into 18 types shown below. Please refer to the following pages for the block diagrams of each port type. Type GP port Function 1 Function ...
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Type T1 Type general-purpose input/ output port with pull-up. Pull-up and output are disabled during reset. PxPUP (Pull-up Control) PxCR (Output Control) Px (Output Latch) PxIE (Input Control) Port Read Under development Drive Disable In STOP ...
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Input/Output Ports 9.3.3 Type T2 Type general-purpose input/ output port with pull-up used to input function data as well. Output is disabled during reset. Under development Page128 TMPM330 ...
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Type T3 Type general-purpose input/ output port with pull-up used to input function data as well. Pull-up and output are disabled during reset. Under development Page129 TMPM330 ...
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Input/Output Ports 9.3.5 Type T4 Type general-purpose input/ output port with open drain used to input function data as well. Pull-up and output are disabled during reset. Under development Page130 TMPM330 ...
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Type T5 Type general-purpose input/ output port with pull-up used to input function data as well. During reset, it functions as an input port for a BOOT signal and pull-up and output are disabled. ...
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Input/Output Ports 9.3.7 Type T6 Type general-purpose port with pull-down used to input function data as well. Output is disabled during reset. PxPDN (Pull-down Control) PxCR (Output Control) PxFR1 (Function Control) Px (Output Latch) ...
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Type T7 Type general-purpose input/ output port with pull-up used to input interrupts as well. Pull-up and output are disabled during reset. To use the external interrupt input for releasing STOP mode, select this ...
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Input/Output Ports 9.3.9 Type T8 Type general-purpose input/ output port with pull-up and open drain used to input interrupts as well. Pull-up and output are disabled during reset. To use the external interrupt input ...
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Type T9 Type general-purpose input/ output port with pull-up used to output function data as well. Pull-up and output are disabled during reset. Under development Page135 TMPM330 ...
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Input/Output Ports 9.3.11 Type T10 Type T10 is a general-purpose input/ output port with pull-up and open drain used to output function data as well. Pull-up and output are disabled during reset. PxPUP (Pull-up Control) PxCR (Output ...
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Type T11 Type T11 is a general-purpose input/ output port with pull-up used to output function data as well. The function output is controlled by an enable signal. If enabled, the function data is output. Pull-up and ...
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Input/Output Ports 9.3.13 Type T12 Type T12 is a general-purpose input/ output port with pull-up used to input/ output function data as well. The function output is controlled by an enable signal. If enabled, the function data ...
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Type T13 Type T13 is a general-purpose input/ output port with pull-up and open drain used to input/output function data as well. Pull-up and output are disabled during reset. Under development Page139 TMPM330 ...
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Input/Output Ports 9.3.15 Type T14 Type T14 is a general-purpose input/ output port used to input/output function data as well. Output is disabled during reset. (Note) PK0 that uses Type Nch open drain port. ...
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Type T15 Type T15 is a general-purpose input/ output port with pull-up used to output two kinds of function data as well. Pull-up and output are disabled during reset. Under development Page141 TMPM330 ...
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Input/Output Ports 9.3.17 Type T16 Type T16 is a general-purpose input/ output port with pull-up and open drain used to communicate two kinds of function data (function 1: input and output, function 2: input) as well. Pull-up ...
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Type T17 Type general-purpose input port with pull-up used to input analog signals for A/D converter. Pull-up is disabled during reset. PxPUP (Pull-up Control) PxIE (Input Control) Port Read Analog Input Under development Drive ...
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Input/Output Ports 9.3.19 Type T18 Type general-purpose input port with pull-up used to input function data and analog signals for A/D converter as well. Pull-up is disabled during reset. Under development Page144 TMPM330 ...
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Timer/Event Counters (TMRBs) 10.1 Outline Each of the ten channels (TMRB0 through TMRB9) has a multi-functional 16-bit timer/event counter. TMRBs operate in the following four operation modes: • 16-bit interval timer mode • 16-bit event counter mode • ...
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Timer/Event Counters (TMRBs) 10.2 Differences in the Specifications Each channel (TMRB0 through TMRB9) functions independently and the channels operate in the same way, except for the differences in their specifications as shown in Table 10-1 and Table 10-2 ...
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Under development Table 10-2 Differences in the Specifications of TMRB Modules (2) Specification Channel Capture interrupt INTCAP00 TMRB0 INTCAP01 INTCAP10 TMRB1 INTCAP11 INTCAP20 TMRB2 INTCAP21 INTCAP30 TMRB3 INTCAP31 INTCAP40 TMRB4 INTCAP40 INTCAP50 TMRB5 INTCAP51 INTCAP60 TMRB6 INTCAP61 TMRB7 － TMRB8 ...
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Timer/Event Counters (TMRBs) 10.3 Configuration Each channel consists of a 16-bit up-counter, two 16-bit timer registers (one of which is double-buffered, except for TBRB0 with one double-buffered 16-bit timer register), two 16-bit capture registers, two comparators, a capture ...
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Under development Fig. 10-1 TMRB1 Block Diagram (the same applies to channels 0 and 2 through 9) Up-do wn interrupt output Register 1 interrupt output Register 0 interrupt output Overfl ow interrupt output Underfl ow interrupt output Match detection Page149 ...
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Timer/Event Counters (TMRBs) 10.4 Registers 10.4.1 TMRB registers Table 10-3 shows the register names and addresses of each channel. Channel Specification Timer enable register TB0EN Timer RUN register TB0RUN Timer control register TB0CR Timer mode register TB0MOD Timer ...
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Under development Table 10-3 TMRB registers (2/2) Channel Specification Timer enable register TB8EN Timer RUN register TB8RUN Timer control register TB8CR Timer mode register TB8MOD Timer flip-flop control TB8FFCR 0x4001_0210 register Register Timer status register TB8ST names (addresses Interrupt mask ...
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Timer/Event Counters (TMRBs) 10.4.1.1 TMRBn enable register (channels 0 through 9) 31 TBnEN bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 ...
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TMRB RUN register (channels 0 through 9) 31 bit Symbol TBnRUN (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After reset ...
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Timer/Event Counters (TMRBs) 10.4.1.3 TMRB control register (channels 0 through 9) 31 bit Symbol TBnCR (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 ...
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TMRB mode register (channels 0 thorough 9) 31 TBnMOD bit Symbol (0x4001_0xxC) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write R After ...
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Timer/Event Counters (TMRBs) 10.4.1.5 TMRB flip-flop control register (channels 0 through 9) 31 bit Symbol TBnFFCR (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 ...
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TMRB status register (channels 0 through 9) 31 bit Symbol TBnST (0x4001_0xx4) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 7 bit Symbol Read/Write After reset ...
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Timer/Event Counters (TMRBs) 10.4.1.7 TMRB interrupt mask register (channels 0 through 9) 31 TBnIM bit Symbol (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol Read/Write R After reset 0 ...
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TMRB read capture register (channels 0 through 9) 31 TBnUC bit Symbol (0x4001_0xxC) Read/Write After reset 23 bit Symbol Read/Write After reset 15 UCn15 bit Symbol Read/Write After reset Function UCn7 bit Symbol Read/Write After reset Function Under development ...
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Timer/Event Counters (TMRBs) 10.4.1.9 TMRB timer register (channels 0 through 9) 31 TBnRG0 bit Symbol (0x4001_0xx0) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBnRG01 5 Read/Write After reset Function ...
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TMRB capture register (channels 0 through 9) 31 bit Symbol TBnCP0 (0x4001_0xx8) Read/Write R After reset 0 23 bit Symbol Read/Write R After reset 0 15 bit Symbol TBnCP01 5 Read/Write After reset Function 7 bit Symbol TBnCP07 Read/Write ...
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Timer/Event Counters (TMRBs) Under development Page162 TMPM330 ...
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Description of Operations for Each Circuit The channels operate in the same way, except for the differences in their specifications as shown in Table 10-1 and Table 10-2. Therefore, the operational descriptions here are only for channel 0. 10.5.1 ...
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Timer/Event Counters (TMRBs) Table 10-4 Prescaler Output Clock Resolutions @fc = 40MHz Release Clock gear peripheral value clock <GEAR2:0> <FPSEL> 000 (fc) 100(fc/2) 0 (fgear) 101(fc/4) 110(fc/8) 000 (fc) 100(fc/2) 1 (fc) 101(fc/4) 110(fc/8) Under development Select prescaler ...
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The prescaler output clock φTn must be selected so that φTn<fsys is satisfied (so (Note 1) that φTn is slower than fsys). (Note 2) Do not change the clock gear while the timer is operating. (Note 3) “⎯“ denotes a ...
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Timer/Event Counters (TMRBs) Table 10-5 Prescaler Output Clock Resolutions Release Clock gear peripheral value clock <GEAR2:0> <FPSEL 000 (fc) 100(fc/2) 0 (fgear) 101(fc/4) 110(fc/8) 000 (fc) 100(fc/2) 1 (fc) 101(fc/4) 110(fc/8) Under development Select prescaler Prescaler output clock ...
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The prescaler output clock φTn must be selected so that φTn<fsys is satisfied (so (Note 1) that φTn is slower than fsys). (Note 2) Do not change the clock gear while the timer is operating. (Note 3) “⎯“ denotes a ...
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Timer/Event Counters (TMRBs) 10.5.2 Up-counter (UC0) UC0 is a 16-bit binary counter. • Source clock UC0 source clock, specified by types - φT1, φT4 and φT16 - of prescaler output clock or the external clock of the TB0IN0 ...
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Under development • Register setting 1) When not using double-buffering To write data to the timer registers, either a 2-byte data transfer instruction or a 1-byte data transfer instruction written twice in the order of low-order 8 bits followed by ...
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Timer/Event Counters (TMRBs) 10.5.4 Capture This is a circuit that controls the timing of latching values from the UC0 up-counter into the TB0CP0 and TB0CP1 capture registers. The timing with which to latch data is specified by TB0MOD ...
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Description of Operations for Each Mode 10.6.1 16-bit Interval Timer Mode -Generating interrupts at periodic cycles To generate the INTTB0 interrupt, specify a time interval in the TB0RG1 timer register. 10.6.2 16-bit Event Counter Mode It is possible to ...
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Timer/Event Counters (TMRBs) 10.6.3 16-bit Programmable Square Wave Output Mode (PPG) Square waves with any frequency and any duty (programmable square waves) can be output. The output pulse can be either low-active or high-active. Programmable square waves can ...
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The block diagram of this mode is shown below. Selector TB0IN0 φT1 φT4 φT16 Selector TB0RG0-WR TB0CR<TB0WBF> Fig. 10-4 Block Diagram of 16-bit PPG Mode Each register in the 16-bit PPG output mode must be programmed as listed below. 7 ...
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Timer/Event Counters (TMRBs) 10.7 Timer synchronous mode This mode enables the timers to start synchronously. If the mode is used with PPG output, the output can be applied to drive a motor. Use of the timer synchronous mode ...
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Applications using the Capture Function The capture function can be used to develop many applications, including those described below: One-shot pulse output triggered by an external pulse Frequency measurement Pulse width measurement Time difference measurement One-shot pulse output triggered ...
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Timer/Event Counters (TMRBs delay is not required, TB5FF0 is reversed when data is taken into TB5CP0, and TB5RG1 is set to the sum of the TB5CPO value (c) and the one-shot pulse width (p ...
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Pulse width measurement By using the capture function, the “H” level width of an external pulse can be measured. Specifically, by putting free-running state using the prescaler output clock, an external pulse is input through the TB5IN0 ...
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Timer/Event Counters (TMRBs) Time Difference Measurement The up-counter (UC5) is made to count up by putting free-running state using the prescaler output clock. The value of UC5 is taken into the capture register (TB5CP0) at ...
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Serial Channel (SIO) 11.1 Features This device has three serial I/O channels: SIO0 to SIO2. Each channel operates in either the UART mode (asynchronous communication) or the I/O interface mode (synchronous communication) which is selected by the user. I/O ...
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Serial Channel (SIO) Table 11-1 Difference in the Specifications of SIO Modules Pin name Interrupt Enable register Transmit/ receive buffer register Control register Mode control register 0 Baud rate generator control Baud rate generator control 2 Mode control Register ...
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Mode 0 (I/O Interface mode) /LSB first bit Transmission direction • Mode 0 (I/O Interface mode) /MSB first bit 7 Transmission direction • Mode 1 (7 bits UART mode) Without parity start bit ...
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Serial Channel (SIO) 11.2 Block Diagram (Channel 0) Prescaler φ φT1 φT4 Serial clock generation circuit SC0BRCR <BR0CK1, 0> SC0BRCR <BR0S3: 0> φT1 φT4 φT16 φT64 Baud rate generator f /2 SYS SCLK0 ...
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Operation of Each Circuit (Channel 0) 11.3.1 Prescaler The device includes a 7-bit prescaler to generate necessary clocks to drive SIO0. The input clock φ the prescaler is selected by SYSCR1 of CG <PRCK2:0> to provide the ...
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Serial Channel (SIO) Table 11-2 Clock Resolution to the Baud Rate Generator Clear Prescaler clock Clock gear peripheral selection value clock <PRCK2:0> <GEAR2:0> <FPSEL> 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 000 (fc) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 100(fc/2) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) ...
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The prescaler output clock φTn must be selected so that the relationship (Note 1) “φTn < fsys” is satisfied (so that φTn is slower than fsys). (Note 2) Do not change the clock gear while SIO is operating. (Note 3) ...
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Serial Channel (SIO) Table 11-3 Clock Resolution to the Baud Rate Generator Clear Clock gear Prescaler clock periferal clock value <FPSEL> <GEAR2:0> <PRCK2:0> 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 000 (fc) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) 000(fperiph/1) 001(fperiph/2) 010(fperiph/4) 100(fc/2) 011(fperiph/8) 100(fperiph/16) 101(fperiph/32) 0 ...
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The prescaler output clock φTn must be selected so that the relationship (Note 1) “φTn < fsys” is satisfied (so that φTn is slower than fsys). (Note 2) Do not change the clock gear while SIO is operating. (Note 3) ...
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Serial Channel (SIO) 11.3.2 Baud Rate Generator The baud rate generator generates transmit and receive clocks to determine the serial channel transfer rate. The baud rate generator uses either the φ T1, φ T4, φ T16 or φ T64 ...