TMPM330FWFG Toshiba, TMPM330FWFG Datasheet - Page 382
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TMPM330FWFG
Manufacturer Part Number
TMPM330FWFG
Description
Microcontrollers (MCU) MCU w/ ARM Cortex-M3 128K FLASH, 8K SRAM
Manufacturer
Toshiba
Specifications of TMPM330FWFG
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
128K
Rom Type
Flash
Ram (kbytes)
8K
Number Of Pins
100
Package
LQFP(14×14)
Vcc
3V
Cpu Mhz
40
Ssp (ch) Spi
-
I2c/sio (ch)
3
Uart/sio (ch)
3
Usb
-
Can
-
Ethernet
-
External Bus Interface
-
Cs/wait Controller (ch)
-
Dma Controller
-
10-bit Da Converter
-
10-bit Ad Converter
12
12-bit Ad Converter
-
16-bit Timer / Counter
10
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / Rohs Status
Details
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13.4
Operation Description
(4)
are required. If multiple factors are specified, reception is completed by the factor detected first. Make
sure to configure the reception completion settings.
To complete data reception, settings of detecting the maximum data bit cycle and excess low width
Settings of Reception Completion
1. Completed by a maximum data bit cycle
2. Completed by excess low width
RMCxRCR2 <RMCDMAX[7:0]> bits.
the <RMCDMAX[7:0]> bits, a maximum data bit cycle is detected.
<RMCLL[7:0]> bits.
excess low width is detected. The detection completes reception and generates an interrupt.
To complete reception by detecting a maximum data bit cycle, you need to configure the
If the falling edge of the data bit cycle isn't monitored after time specified as threshold in
The detection completes reception and generates an interrupt.
After interrupt inputs generated, RMCxRSTAT< RMCDMAXIF > bit is set to "1".
To complete reception by detecting the low width, you need to configure the RMCxRCR2
After the falling edge of the data bit is detected, if the signal stays low longer than specified,
After interrupt inputs generated, RMCxRSTAT<RMCLOIF> bit is set to "1."
If the falling edge of the data bit cycle is not monitored after time
specified as threshold,a maximum data bit cycle is detected.
The detection completes reception and generates an interrupt.
Threshold:<RMCDMAX[7:0]>
Threshold:<RMCLL[7:0]>
Excess low width is detected when signal
stay low longer than specified.
Page 362
The maximum data bit cycle interrupt
Excess low width
detection interrupt.
TMPM330FDFG/FYFG/FWFG
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