Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 106

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

Multi-Channel PWM Timer
Architecture
PS028702-1210
The Z16FMC includes a Multi-Channel PWM optimized for motor control applications.
The PWM includes the following features:
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The PWM unit consists of a master timer to generate the modulator time base and six inde-
pendent compare registers to set the PWM for each output. The six outputs are designed to
provide control signals for inverter drive circuits. The outputs are grouped into pairs con-
sisting of a high-side driver and a low-side driver output. The output pairs are programma-
ble to operate independently or as complementary signals.
In complementary output mode, a programmable dead-time is inserted to ensure non-over-
lapping signal transitions. The master count and compare values feed into modulator logic
which generates the proper transitions in the output states. Output polarity and fault/off-
state control logic allows programming of the default off-states which forces the outputs to
a safe state in the event a fault in the motor drive is detected. Figure 11 displays the archi-
tecture of the PWM modulator.
Six independent PWM outputs or three complementary PWM output pairs.
Programmable deadband insertion for complementary output pairs.
Edge-aligned or center-aligned PWM signal generation.
PWM off-state is an option bit programmable.
PWM outputs driven to off-state on System Reset.
Asynchronous disabling of PWM outputs on system fault. Outputs are forced to off-
state.
Fault inputs generate pulse-by-pulse or hard shutdown.
12-bit reload counter with 1, 2, 4, or 8 programmable clock prescaler.
High current source and sink on all PWM outputs.
PWM pairs used as general purpose inputs when outputs are disabled.
ADC synchronized with PWM period.
Synchronization for current-sense sample and hold.
Narrow pulse suppression with programmable threshold.
P R E L I M I N A R Y
Z16FMC Series Motor Control MCUs
Multi-Channel PWM Timer
Product Specification
84