Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 207

• Manufacturer Part Number: Z16FMC64AG20EG
• Description: Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
• Manufacturer: Zilog
• Series: Z16FMCr

Specifications of Z16FMC64AG20EG

• Processor Series: Z16FMC
• Core: ZNEO
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• Development Tools By Supplier: Z16FMC28200KITG
• Minimum Operating Temperature: - 40 C
• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Eeprom Size: -
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PS028702-1210
Slave Transactions
22. Software responds by reading the I
23. The I
24. If there are more bytes to transfer, the I
25. The I
26. Software responds by setting the STOP bit of the I
27. A STOP condition is sent to the I
The following sections describe Read and Write transactions to the I
ured for 7-bit and 10-bit SLAVE modes.
Slave Address Recognition
The following slave address recognition options are supported:
Slave 7-bit address recognition mode.
troller is configured for Master/Slave or Slave 7-bit address mode, the hardware detects a
match to the 7-bit slave address defined in the I2CSLVAD Register and generates the
Slave Address Match interrupt (
automatically responds during the acknowledge phase with the value in the
I2CCTL Register.
Slave 10-bit address recognition mode.
controller is configured for Master/Slave or Slave 10-bit address mode, the hardware
detects a match to the 10-bit slave address defined in the I2CMODE and I2CSLVAD reg-
isters and generates the Slave Address Match interrupt (
The I
in the
General Call and STARTBYTE address recognition.
address phase and the controller is configured for Master/Slave or Slave in either 7- or 10-
bit address mode, the hardware detects a match to the General Call Address or START
byte and generates the Slave Address Match interrupt. A General Call Address is a 7-bit
address of all 0’s with the R/W bit = 0. A START byte is a 7-bit address of all 0’s with the
R/W bit = 1. The
I2CISTAT Register distinguishes a General Call Address from a START byte (= 0 for
General Call Address). For a General Call Address, the I
responds during the address acknowledge phase with the value in the
I2CCTL Register. If software processes the data bytes associated with the
bit is optionally set following the SAM interrupt to allow software to examine each
final byte, software must set the
based on the
2
NAK
C Controller automatically responds during the acknowledge phase with the value
2
2
C Controller sends an Acknowledge or Not Acknowledge to the I
C Controller generates a NAK interrupt (NCKI bit in I2CISTAT).
bit of the I2CCTL Register.
NAK
SAM
bit.
and
GCA
P R E L I M I N A R Y
bits are set in the I2CISTAT Register. The
SAM
NAK
bit = 1 in I2CISTAT Register). The I
2
C Slave.
2
C Data Register. If the next data byte is to be the
bit of the I
If
If
2
IRM
C Controller returns to step 18.
IRM
Z16FMC Series Motor Control MCUs
= 0 during the address phase and the con-
= 0 during the address phase and the
2
C Control Register.
2
C Control Register.
SAM
If
2
C Controller automatically
GCE
bit = 1 in I2CISTAT register).
I2C Master/Slave Controller
= 1 and
Product Specification
2
C Controller config-
NAK
IRM
2
GCA
RD
C Controller
bit of the
= 0 during the
NAK
2
C Slave
bit in the
bit, the
bit of the
IRM
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